{"title":"模块生成器中多级逻辑单元优化方法","authors":"P. Poechmueller, M. Glesner","doi":"10.1109/GLSV.1991.143980","DOIUrl":null,"url":null,"abstract":"The authors present new ideas in the field of multilevel optimization for automatic logic macrocell synthesis. The proposed new approach performs a quasi parallel optimization of very different and complex tasks via a simulated annealing based expert system. A true design space exploration is achieved, finding the best solution with respect to a certain cost-function which takes into account actual design parameters like speed, area, power, and not only indirect parameters like number of literals, etc. A small prototype software system had been implemented and it is shown how this new approach, e.g. can be used within a module generator.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An approach for multilevel logic cell optimization in module generators\",\"authors\":\"P. Poechmueller, M. Glesner\",\"doi\":\"10.1109/GLSV.1991.143980\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The authors present new ideas in the field of multilevel optimization for automatic logic macrocell synthesis. The proposed new approach performs a quasi parallel optimization of very different and complex tasks via a simulated annealing based expert system. A true design space exploration is achieved, finding the best solution with respect to a certain cost-function which takes into account actual design parameters like speed, area, power, and not only indirect parameters like number of literals, etc. A small prototype software system had been implemented and it is shown how this new approach, e.g. can be used within a module generator.<<ETX>>\",\"PeriodicalId\":261873,\"journal\":{\"name\":\"[1991] Proceedings. First Great Lakes Symposium on VLSI\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1991] Proceedings. First Great Lakes Symposium on VLSI\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/GLSV.1991.143980\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1991] Proceedings. First Great Lakes Symposium on VLSI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GLSV.1991.143980","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An approach for multilevel logic cell optimization in module generators
The authors present new ideas in the field of multilevel optimization for automatic logic macrocell synthesis. The proposed new approach performs a quasi parallel optimization of very different and complex tasks via a simulated annealing based expert system. A true design space exploration is achieved, finding the best solution with respect to a certain cost-function which takes into account actual design parameters like speed, area, power, and not only indirect parameters like number of literals, etc. A small prototype software system had been implemented and it is shown how this new approach, e.g. can be used within a module generator.<>