{"title":"密集的串并联电路布局","authors":"M. Langston, S. Ramachandramurthi","doi":"10.1109/GLSV.1991.143935","DOIUrl":null,"url":null,"abstract":"The authors address the question 'when do three tracks suffice for the gate matrix layout of series-parallel circuits?' and demonstrate that the rather surprising answer appears to be 'almost always.' This is in contrast to the fact that an unbounded number of tracks may be required to layout contrived instances in the worst case. Their approach stems from the novel nonconstructive finite-basis characterization of graphs with k-track layouts for any fixed k.<<ETX>>","PeriodicalId":261873,"journal":{"name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","volume":"183 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Dense layouts for series-parallel circuits\",\"authors\":\"M. Langston, S. Ramachandramurthi\",\"doi\":\"10.1109/GLSV.1991.143935\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The authors address the question 'when do three tracks suffice for the gate matrix layout of series-parallel circuits?' and demonstrate that the rather surprising answer appears to be 'almost always.' This is in contrast to the fact that an unbounded number of tracks may be required to layout contrived instances in the worst case. Their approach stems from the novel nonconstructive finite-basis characterization of graphs with k-track layouts for any fixed k.<<ETX>>\",\"PeriodicalId\":261873,\"journal\":{\"name\":\"[1991] Proceedings. First Great Lakes Symposium on VLSI\",\"volume\":\"183 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1991] Proceedings. First Great Lakes Symposium on VLSI\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/GLSV.1991.143935\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1991] Proceedings. First Great Lakes Symposium on VLSI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GLSV.1991.143935","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The authors address the question 'when do three tracks suffice for the gate matrix layout of series-parallel circuits?' and demonstrate that the rather surprising answer appears to be 'almost always.' This is in contrast to the fact that an unbounded number of tracks may be required to layout contrived instances in the worst case. Their approach stems from the novel nonconstructive finite-basis characterization of graphs with k-track layouts for any fixed k.<>