Gate level representation of ECL circuits for fault modeling

Abstract

Bipolar emitter coupled logic (ECL) devices can now be fabricated at high densities and lower power consumption. With the achievement of low power and high densities, ECL technology is expected to be used widely in high performance digital circuits. This necessitates the need for obtaining optimum gate level models for ECL circuits. A simple technique to obtain a gate level model of an ECL circuit is presented. The gate level models obtained for 1-level and 2-level ECL using the transformation rules presented are the same as the fault models that provide higher coverage of physical failures.<>