Transition count testing of CMOS combinational circuits

Abstract

An optimal, robust transition count test generation for testing stuck-open faults in CMOS combinational circuits is presented in this paper. Procedures to optimize conventional stuck-open fault test sets have been developed. The use of fault folding graphs as a tool, to generate optimal test sequences, has been illustrated. Both non-reconvergent and reconvergent, irredundant, circuits are treated,.<>