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A 2V BiCMOS receiver chip for L-S-C band personal networks 一种用于L-S-C波段个人网络的2V BiCMOS接收芯片
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520699
M. Madihian, E. Bak, K. Imai, H. Yoshida, Y. Kinoshita, T. Yamazaki
{"title":"A 2V BiCMOS receiver chip for L-S-C band personal networks","authors":"M. Madihian, E. Bak, K. Imai, H. Yoshida, Y. Kinoshita, T. Yamazaki","doi":"10.1109/VLSIC.1995.520699","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520699","url":null,"abstract":"This paper concerns with the design and performance results of a receiver chip developed for personal networks applications utilizing a BiCMOS technology. The receiver, which integrates a bipolar RF amplifier, a BiCMOS simplified Gilbert mixer, and an NMOS IF amplifier, on a single chip, is designed to operate at 2 V over 1.8-5.4 GHz frequency band with a total power dissipation of 18 mW. Maximum conversion gain, LO-IF and RF-IF isolation are, respectively, 34 dB, 40 dB, and 32 dB.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133986504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 3.3 V 16 Mbit DRAM-compatible flash memory 3.3 V 16mbit dram兼容快闪存储器
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520688
R. Fackenthal, P. Kwong, D. Mills, S. Sambandan, S. Sweha
{"title":"A 3.3 V 16 Mbit DRAM-compatible flash memory","authors":"R. Fackenthal, P. Kwong, D. Mills, S. Sambandan, S. Sweha","doi":"10.1109/VLSIC.1995.520688","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520688","url":null,"abstract":"A new 16 Mb (1 Mbit/spl times/16) flash memory on a 0.6 /spl mu/m CMOS process has been designed, that combines the high-speed code execution capabilities of DRAM with nonvolatile, high-density, updatable code storage of flash memory, thus replacing the traditional redundant memory paradigm with one cost-effective solution. This solution eliminates the need to shadow code from nonvolatile memory to DRAM, thus enabling design of direct-execute code and mass storage memory systems, while the fully DRAM-compatible interface allows glueless design with existing DRAM controllers.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131238547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Low power Gb/s CMOS interfaces 低功耗Gb/s CMOS接口
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520673
Y. Ohtomo, M. Nogawa
{"title":"Low power Gb/s CMOS interfaces","authors":"Y. Ohtomo, M. Nogawa","doi":"10.1109/VLSIC.1995.520673","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520673","url":null,"abstract":"For high-speed digital systems, it is important to develop point-to-point Gb/s interfaces that consume low power during low-transition-rate operation. This paper presents two novel Gb/s CMOS interfaces. One uses an active-pull-up (APU) technique to raise the maximum transmission speed. In the other interface, the transmission wave form is changed from digital to impulse to markedly reduce power consumption at low transition rate.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115350813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A mixed-mode voltage-down converter with impedance adjustment circuitry for low-voltage wide-frequency DRAMs 一种低压宽频dram用带阻抗调节电路的混合模式降压变换器
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520710
T. Ooishi, Y. Komiya, K. Hamade, M. Asakura, K. Yasuda, K. Furutani, T. Kato, H. Hidaka, H. Ozaki
{"title":"A mixed-mode voltage-down converter with impedance adjustment circuitry for low-voltage wide-frequency DRAMs","authors":"T. Ooishi, Y. Komiya, K. Hamade, M. Asakura, K. Yasuda, K. Furutani, T. Kato, H. Hidaka, H. Ozaki","doi":"10.1109/VLSIC.1995.520710","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520710","url":null,"abstract":"In DRAMs a dramatic operation voltage reduction has been realized by the voltage-down converter (VDC) for a low power dissipation and high reliability. However, in the low-voltage and high-frequency domain this technique will see several crucial problems. Besides, the wide-frequency operation (e.g. an extended data output and a synchronous operation) and the variable-load current (e.g, a variable refresh cycle and a changeable data output) are required. This paper proposes VDC circuit techniques for the low-voltage (less than 2.5 V), wide-frequency, and the variable-load current. The mixed-mode VDC (MM-VDC) provides two-modes of current by the analog VDC (A-VDC) and the digital VDC (D-VDC) supply being suitable for the load current. It also reduces the current consumption in the VDC and guarantees stable operation. Moreover, the impedance adjustment circuitry (IAC) controls the current supply capability of the D-VDC according to the load operation frequency to minimize the bounce of the internal power supply level. The MM-VDC can be applicable to low-voltage wide-frequency DRAMs.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"416 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115994967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A novel BiCMOS circuit using a base boost technique for low voltage application 采用基极升压技术的新型低压BiCMOS电路
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520714
K. Ohhata, H. Nambu, K. Kanetani, T. Masuda, T. Kusunoki, N. Homma
{"title":"A novel BiCMOS circuit using a base boost technique for low voltage application","authors":"K. Ohhata, H. Nambu, K. Kanetani, T. Masuda, T. Kusunoki, N. Homma","doi":"10.1109/VLSIC.1995.520714","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520714","url":null,"abstract":"The high-speed performance of BiCMOS logic circuits is mostly lost under low-power supply voltage conditions. This is because the output swing is decreased due to the built-in voltage of the emitter-base junction (VBE). To overcome this problem, full-swing operation must be achieved. Transiently Saturated Full-Swing (TS-FS) BiCMOS logic circuit has achieved full-swing operation. This circuit, however, requires a high-performance pnp transistor, therefore, it introduces a drawback of high manufacturing cost. This paper proposes a novel BiCMOS logic circuit for low voltage application. It can operate at supply voltages as low as 1-1.5 V without a pnp transistor.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124104434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A novel sense amplifier for flexible voltage operation NAND flash memories 一种用于柔性电压操作NAND闪存的新型感测放大器
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520690
H. Nakamura, J. Miyamoto, K. Imamiya, Y. Iwata
{"title":"A novel sense amplifier for flexible voltage operation NAND flash memories","authors":"H. Nakamura, J. Miyamoto, K. Imamiya, Y. Iwata","doi":"10.1109/VLSIC.1995.520690","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520690","url":null,"abstract":"This paper proposes a new bit-by-bit verify circuit for application in NAND flash memories. The Sense Amplifier (S/A) employed confers two benefits: flexible power supply voltage (ex. 3 V or 5 V) operation with a high noise immunity and an intelligent page copy function. The benefits are very useful to the flash memory card or system and accelerate the replacement of magnetic memories by flash memories. The S/A has been successfully implemented in the commercial version of the 32 Mbit NAND-EEPROM, in which the S/A is newly introduced in comparison with the prototype version.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114569764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 500 MHz 1-stage 32 bit ALU with self-running test circuit 带有自运行测试电路的500mhz 1级32位ALU
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520664
T. Yoshida, G. Matsubara, S. Yoshioka, H. Tago, S. Suzuki, N. Goto
{"title":"A 500 MHz 1-stage 32 bit ALU with self-running test circuit","authors":"T. Yoshida, G. Matsubara, S. Yoshioka, H. Tago, S. Suzuki, N. Goto","doi":"10.1109/VLSIC.1995.520664","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520664","url":null,"abstract":"A 500 MHz 1-stage 32 bit ALU has been designed and fabricated using 0.3 /spl mu/m CMOS process. Main features are a 1.56 ns DPL (Double path-transistor logic) adder and a compact barrel shifter using a newly developed 4-input MUX scheme. A BIST (built-in self test) circuit enables 500 MHz real-time testing. The chip size is 1 mm/spl times/0.38 mm.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133740438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A bit-parallel block-parallel functional memory type parallel processor LSI for fast addition and multiplication 用于快速加法和乘法的位并行块并行功能存储器型并行处理器LSI
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520685
K. Kobayashi, H. Onodera, K. Tamaru
{"title":"A bit-parallel block-parallel functional memory type parallel processor LSI for fast addition and multiplication","authors":"K. Kobayashi, H. Onodera, K. Tamaru","doi":"10.1109/VLSIC.1995.520685","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520685","url":null,"abstract":"We developed a new LSI chip based on the bit-parallel block-parallel functional memory type parallel processor (BPBP FMPP) architecture. The chip includes 1024 bit (32 word/spl times/32 bit) memory storage cells on a 45 mm/sup 2/ die using a 1.2 /spl mu/m CMOS process, and achieves 5 MHz clock rate at the worst case simulation. The BPBP FMPP LSI has capabilities of addition in O(1) and multiplication in O(m), where m represents the number of bits. Such functionality enhances its applicability into vast fields, where numerical operations are required.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131752041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 0.25 mW sigma-delta modulator for voice-band applications 一个0.25 mW的sigma-delta调制器，用于语音波段应用
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520676
S. Kiriaki
{"title":"A 0.25 mW sigma-delta modulator for voice-band applications","authors":"S. Kiriaki","doi":"10.1109/VLSIC.1995.520676","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520676","url":null,"abstract":"A very low power and high resolution analog to digital converter has been developed for voice-band applications. It employs a third-order cascaded sigma-delta modulator and operates with supply range from 2 V to 5 V. When this modulator is used at an oversampling ratio (OSR) of 64 and clock frequency of 500 kHz, it achieves 81.5 dB dynamic range and 77 dB peak signal-to-noise plus distortion ratio (SNDR). The power required for this performance is only 0.25 mW at 2 V power-supply voltage.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132016304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
CMOS stress sensor circuits using piezoresistive field-effect transistors (PIFETs) 采用压阻场效应晶体管(pifet)的CMOS应力传感器电路
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520680
R. Jaeger, R. Ramani, J. Suhling, Y. Kang
{"title":"CMOS stress sensor circuits using piezoresistive field-effect transistors (PIFETs)","authors":"R. Jaeger, R. Ramani, J. Suhling, Y. Kang","doi":"10.1109/VLSIC.1995.520680","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520680","url":null,"abstract":"CMOS analog stress sensor circuits based upon the piezoresistive behavior of MOSFETs are proposed. On the (100) surface, these circuits provide temperature compensated output voltages and currents that are proportional to the inplane normal stress difference (/spl sigma//sub 11//sup -/-/spl sigma//sub 22//sup -/) and the in-plane shear stress /spl sigma//sub 12//sup -/ The circuits offer high sensitivity to stress, highly localized stress measurement and provide direct voltage or current outputs, eliminating the need for tedious /spl Delta/R/R measurements required with more traditional resistor rosettes.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"448 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123275110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 49
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