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Capacitance coupling immune, transient sensitive accelerator for resistive interconnection signals of sub-quarter micron ULSI 用于亚四分之一微米ULSI电阻互连信号的抗电容耦合、瞬态灵敏加速器
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520674
Tomofumi lima, M. Mizuno, T. Horiuchi, M. Yamashina
{"title":"Capacitance coupling immune, transient sensitive accelerator for resistive interconnection signals of sub-quarter micron ULSI","authors":"Tomofumi lima, M. Mizuno, T. Horiuchi, M. Yamashina","doi":"10.1109/VLSIC.1995.520674","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520674","url":null,"abstract":"We have developed a new circuit scheme that reduces the delay time caused by large interconnection resistances. Also, this circuit immunizes cross talk caused at scaled interconnections of sub-quarter micron ULSIs. The reduction of the delay time is 60% and output fluctuation is improved to negligibly small magnitude. The proposed circuit can be applied to bi-directional signal communication without adding further hardware and is extremely useful for sub-quarter micron ULSIs with scaled resistive interconnections.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115962519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
A parallel processor for neural networks 用于神经网络的并行处理器
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520695
P. Lee, A. Sartori, G. Tecchiolli, A. Zorat
{"title":"A parallel processor for neural networks","authors":"P. Lee, A. Sartori, G. Tecchiolli, A. Zorat","doi":"10.1109/VLSIC.1995.520695","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520695","url":null,"abstract":"A deeply-pipelined digital parallel processor for the implementation of Multi-Layer Perceptrons is presented. It employs high-speed limited-precision integer arithmetic and allows good recognition performance in combination with a novel training algorithm. Internal dynamic RAM is provided for storage of the weights. The chip achieves a performance of 600 million multiply-and-accumulate operations per second and requires a silicon area of 70 mm/sup 2/ in a 1.2-/spl mu/m CMOS technology.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122607678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Fault-tolerant designs for 256 Mb DRAM 256 Mb DRAM的容错设计
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520708
T. Kirihata, Y. Watanabe, H. Wong, J. DeBrosse, M. Yoshida, D. Kato, S. Fujii, M. Wordeman, P. Poechmueller, Stephen A. Parke, Y. Asao
{"title":"Fault-tolerant designs for 256 Mb DRAM","authors":"T. Kirihata, Y. Watanabe, H. Wong, J. DeBrosse, M. Yoshida, D. Kato, S. Fujii, M. Wordeman, P. Poechmueller, Stephen A. Parke, Y. Asao","doi":"10.1109/VLSIC.1995.520708","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520708","url":null,"abstract":"Conventional redundancy architecture employs a repair region in each block, and therefore has disadvantages: (1) each block must have at least one (preferably two) redundant row and column, increasing design space; (2) grouped or clustered fails are difficult to repair; (3) a cross fail (WL/BL short-circuit) increases the stand-by current, causing a standby fail. Fault-tolerant designs were developed for a 256 Mb DRAM to overcome these problems by means of a redundancy block, interchangeable Master DQ's (MDQ's), and a current limiter.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114411990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
Pass transistor based gate array architecture 通过基于晶体管的门阵列结构
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520716
Y. Sasaki, K. Yano, M. Hiraki, K. Rikino, M. Miyamoto, T. Matsuura, T. Nishida, K. Seki
{"title":"Pass transistor based gate array architecture","authors":"Y. Sasaki, K. Yano, M. Hiraki, K. Rikino, M. Miyamoto, T. Matsuura, T. Nishida, K. Seki","doi":"10.1109/VLSIC.1995.520716","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520716","url":null,"abstract":"This paper describes a completely new gate array architecture that fully exploits inherent advantages of pass transistor logic which a conventional architecture can not. In implementing SRAMs, our gate array achieves a 1.5 times higher density than a conventional gate array due to its different size transistors in the basic cell. An 8/spl times/8 b multiplier designed with this gate array using 0.4-/spl mu/m CMOS process achieves a multiplication time of 12.7 ns and dissipates 480 /spl mu/W with the supply voltage of 1.2 V. A 1.2 V 9 ns 1 kb SRAM was also designed with the same gate array.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133686598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Combined air humidity and flow CMOS microsensor with on-chip 15 bit sigma-delta A/D interface 结合空气湿度和流量CMOS微传感器，片上15位sigma-delta A/D接口
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520681
P. Malcovati, A. Haberli, F. Mayer, O. Paul, F. Maloberti, H. Baltes
{"title":"Combined air humidity and flow CMOS microsensor with on-chip 15 bit sigma-delta A/D interface","authors":"P. Malcovati, A. Haberli, F. Mayer, O. Paul, F. Maloberti, H. Baltes","doi":"10.1109/VLSIC.1995.520681","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520681","url":null,"abstract":"In this paper we present a batch fabricated multi-sensor chip for building control applications. A capacitive relative humidity sensor and a thermoelectric gas flow sensor have been integrated on a single chip together with a second order sigma-delta A/D converter, achieving 15 bit resolution. Both sensors are connected to the same sigma-delta modulator, without requiring any additional readout circuit. We report experimental results on a prototype realized with a commercial 2 /spl mu/m CMOS process.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"38 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122508165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A crossing charge recycle refresh scheme with a separated driver sense-amplifier for Gb DRAMs Gb dram中带分离驱动感测放大器的交叉电荷循环刷新方案
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520705
I. Naritake, T. Sugibayashi, S. Utsugi, T. Murotani
{"title":"A crossing charge recycle refresh scheme with a separated driver sense-amplifier for Gb DRAMs","authors":"I. Naritake, T. Sugibayashi, S. Utsugi, T. Murotani","doi":"10.1109/VLSIC.1995.520705","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520705","url":null,"abstract":"A crossing charge recycle refresh (CCRR) scheme is proposed for large capacity DRAMs with hierarchical bit-line architecture, which reduces main bit-line charging current to 25% of that of conventional DRAMs. A separated driver sense-amplifier (SDSA) circuit is essential to realize this scheme because it features 11 times shorter charge transfer period than that of conventional sense amplifiers. These circuits are applied to an experimental 1-Gb DRAM.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127265205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 375 MHz 1 /spl mu/m CMOS 8-bit multiplier 一个375 MHz 1 /spl mu/m CMOS 8位乘法器
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520665
R. Rogenmoser, Qiuting Huang
{"title":"A 375 MHz 1 /spl mu/m CMOS 8-bit multiplier","authors":"R. Rogenmoser, Qiuting Huang","doi":"10.1109/VLSIC.1995.520665","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520665","url":null,"abstract":"A signed 8-bit pipelined multiplier has been implemented in a standard 1.0 /spl mu/m CMOS process. It was successfully tested up to 375 MHz. This performance was achieved using the true single-phase clocking technique, fine-grain pipelining, and merging the combinational logic into the pipeline registers.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127397989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
30 GHz static 2:1 frequency divider and 46 Gb/s multiplexer/demultiplexer ICs in a 0.6 /spl mu/m Si bipolar technology 30 GHz静态2:1分频器和46 Gb/s多路复用/解路复用ic，采用0.6 /spl mu/m Si双极技术
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520713
A. Felder, M. Moller, J. Popp, J. Bock, M. Rest, H. Rein, L. Treitinger
{"title":"30 GHz static 2:1 frequency divider and 46 Gb/s multiplexer/demultiplexer ICs in a 0.6 /spl mu/m Si bipolar technology","authors":"A. Felder, M. Moller, J. Popp, J. Bock, M. Rest, H. Rein, L. Treitinger","doi":"10.1109/VLSIC.1995.520713","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520713","url":null,"abstract":"High-speed digital functions realised as a 30 GHz static frequency divider and 46 Gb/s multiplexer and demultiplexer are presented. These ICs demonstrate the speed potential of silicon bipolar technology obtained by optimized combination of well-proven transistor concepts and production technology like process steps in a 0.6 /spl mu/m CMOS production environment. The measured results are record data not only for silicon but, except for the static divider, for all semiconductor technologies.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"64 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126109295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
An on-chip high-voltage generator circuit for EEPROMs with a power supply voltage below 2 V 用于电源电压低于2v的eeprom的片上高压发生器电路
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520692
K. Sawada, Y. Sugawara, S. Masui
{"title":"An on-chip high-voltage generator circuit for EEPROMs with a power supply voltage below 2 V","authors":"K. Sawada, Y. Sugawara, S. Masui","doi":"10.1109/VLSIC.1995.520692","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520692","url":null,"abstract":"We propose an on-chip high-voltage generator circuit for low-voltage EEPROMs composed of a pMOSFET-based charge pump circuit driven by bootstrapped clock generators. The voltage gain per unit stage does not suffer from the threshold voltage drop. The device implemented in a 1.2 /spl mu/m CMOS technology operates as low as 1 V.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131669755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 71
A 286 mm/sup 2/ 256 Mb DRAM with X32 both-ends DQ 286mm /sup 2/ 256mb DRAM，两端DQ为X32
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520707
Y. Watanabe, H. Wong, T. Kirihata, D. Kato, J. DeBrosse, T. Hara, M. Yoshida, H. Mukai, K. Quader, T. Nagai, P. Poechmueller, K. Pfefferl, M. Wordeman, S. Fujii
{"title":"A 286 mm/sup 2/ 256 Mb DRAM with X32 both-ends DQ","authors":"Y. Watanabe, H. Wong, T. Kirihata, D. Kato, J. DeBrosse, T. Hara, M. Yoshida, H. Mukai, K. Quader, T. Nagai, P. Poechmueller, K. Pfefferl, M. Wordeman, S. Fujii","doi":"10.1109/VLSIC.1995.520707","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520707","url":null,"abstract":"The growing market for high performance PCs has created a demand for a new generation of DRAMs with wide bit organization. A wider I/O DRAM is necessary to provide a sufficiently small granularity for the memory system. Hierarchical data-line architectures which transfer many bits over the memory array could potentially be used to provide a wide I/O. However, even using these schemes, chip size must expand to accommodate additional devices and wiring as the I/O width increases. This paper describes a chip architecture which minimizes the die size of wide I/O DRAMs and its application to a 256 Mb DRAM with X32 organization.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115932146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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