Gb dram中带分离驱动感测放大器的交叉电荷循环刷新方案

Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI:10.1109/VLSIC.1995.520705

I. Naritake, T. Sugibayashi, S. Utsugi, T. Murotani

{"title":"Gb dram中带分离驱动感测放大器的交叉电荷循环刷新方案","authors":"I. Naritake, T. Sugibayashi, S. Utsugi, T. Murotani","doi":"10.1109/VLSIC.1995.520705","DOIUrl":null,"url":null,"abstract":"A crossing charge recycle refresh (CCRR) scheme is proposed for large capacity DRAMs with hierarchical bit-line architecture, which reduces main bit-line charging current to 25% of that of conventional DRAMs. A separated driver sense-amplifier (SDSA) circuit is essential to realize this scheme because it features 11 times shorter charge transfer period than that of conventional sense amplifiers. These circuits are applied to an experimental 1-Gb DRAM.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A crossing charge recycle refresh scheme with a separated driver sense-amplifier for Gb DRAMs\",\"authors\":\"I. Naritake, T. Sugibayashi, S. Utsugi, T. Murotani\",\"doi\":\"10.1109/VLSIC.1995.520705\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A crossing charge recycle refresh (CCRR) scheme is proposed for large capacity DRAMs with hierarchical bit-line architecture, which reduces main bit-line charging current to 25% of that of conventional DRAMs. A separated driver sense-amplifier (SDSA) circuit is essential to realize this scheme because it features 11 times shorter charge transfer period than that of conventional sense amplifiers. These circuits are applied to an experimental 1-Gb DRAM.\",\"PeriodicalId\":256846,\"journal\":{\"name\":\"Digest of Technical Papers., Symposium on VLSI Circuits.\",\"volume\":\"27 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-06-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Technical Papers., Symposium on VLSI Circuits.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.1995.520705\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Technical Papers., Symposium on VLSI Circuits.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1995.520705","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

针对分层位线结构的大容量dram，提出了一种交叉电荷循环刷新(cross charge recycle refresh, CCRR)方案，可将主位线充电电流降低到传统dram的25%。分离驱动感测放大器(SDSA)电路是实现该方案的关键，因为它的电荷转移周期比传统感测放大器短11倍。这些电路应用于一个实验性的1gb DRAM。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A crossing charge recycle refresh scheme with a separated driver sense-amplifier for Gb DRAMs

A crossing charge recycle refresh (CCRR) scheme is proposed for large capacity DRAMs with hierarchical bit-line architecture, which reduces main bit-line charging current to 25% of that of conventional DRAMs. A separated driver sense-amplifier (SDSA) circuit is essential to realize this scheme because it features 11 times shorter charge transfer period than that of conventional sense amplifiers. These circuits are applied to an experimental 1-Gb DRAM.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Digest of Technical Papers., Symposium on VLSI Circuits.

自引率

0.00%

发文量