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An analog integrated polyphase filter for a high performance low-IF receiver 一种用于高性能低中频接收机的模拟集成多相滤波器
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520698
J. Crols, M. Steyaert
{"title":"An analog integrated polyphase filter for a high performance low-IF receiver","authors":"J. Crols, M. Steyaert","doi":"10.1109/VLSIC.1995.520698","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520698","url":null,"abstract":"An analog integrated asymmetric polyphase filter is a key building block for the development of a high performance fully integrated low-IF receiver. The asymmetric polyphase filter makes it possible to suppress the mirror signal not at HF, but after quadrature demodulation at a low IF. The most important parameters for the polyphase filter are a high dynamic range and a good mirror signal suppression. This paper reports on the realisation in a 1.2 /spl mu/m CMOS process of a 5th order Butterworth polyphase filter with a bandwidth of 220 kHz centered around 250 kHz. Its measured mirror signal suppression is 64 dB. The active-RC implementation renders a 94.2 dB dynamic range at the input.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115363833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 92
"Graphics synthesizer" for video game applications 视频游戏应用的“图形合成器”
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520683
K. Kutaragi, M. Kwong
{"title":"\"Graphics synthesizer\" for video game applications","authors":"K. Kutaragi, M. Kwong","doi":"10.1109/VLSIC.1995.520683","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520683","url":null,"abstract":"The video game machine, which was first on the scene in the early 1970s, has been progressing with the advance of technology, particularly in semiconductors. Today, the latest video game machine has reached the stage where real-time 3D graphics can be used. In this paper, the necessary conditions for video game machines are described. Also the capability and methodology of the \"PlayStation\" is explained. Finally, LSI requirements for the future video game machine are discussed.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116546316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 100 tap FIR/IIR analog linear-phase lowpass filter 100分接FIR/IIR模拟线性相位低通滤波器
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520700
Qiuting Huang, P. Maguire, T. Burger
{"title":"A 100 tap FIR/IIR analog linear-phase lowpass filter","authors":"Qiuting Huang, P. Maguire, T. Burger","doi":"10.1109/VLSIC.1995.520700","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520700","url":null,"abstract":"A 5 kHz linear-phase lowpass filter is implemented in a 2-/spl mu/m BiCMOS technology as a combination of a sigma-delta front-end, a digital shift register, an SC summer circuit of 50 input capacitors and an SC biquad running at a 1 MHz clock. The measured group delay variation in the passband is less than 1 /spl mu/s and the measured THD is -80 dB for an input sine wave amplitude of 0.7 V at 1 kHz.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126389454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A low-power bipolar circuit for Gbit/s LSIs-current mirror control logic (CMCL) gb /s lsis电流镜像控制逻辑(CMCL)的低功耗双极电路
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520718
K. Kishine, H. Ichino
{"title":"A low-power bipolar circuit for Gbit/s LSIs-current mirror control logic (CMCL)","authors":"K. Kishine, H. Ichino","doi":"10.1109/VLSIC.1995.520718","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520718","url":null,"abstract":"A low-power bipolar circuit for Gbit/s LSIs, Current Mirror Control Logic (CMCL), is proposed. To reduce supply voltage, the lower differential pairs of ECL series-gate circuits are replaced by current mirror circuits. This CMCL circuit achieves 3.1-Gbit/s (D-F/F) and 4.3-GHz (T-F/F) operation with a power supply voltage of -2.0 V and power dissipation of only 1.8 mW/(F/F).","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115847902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 250 mV bit-line swing scheme for a 1 V 4 Gb DRAM 用于1v 4gb DRAM的250mv位线摆振方案
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520704
T. Inaba, D. Takashima, Y. Oowaki, T. Ozaki, S. Watanabe, K. Ohuchi
{"title":"A 250 mV bit-line swing scheme for a 1 V 4 Gb DRAM","authors":"T. Inaba, D. Takashima, Y. Oowaki, T. Ozaki, S. Watanabe, K. Ohuchi","doi":"10.1109/VLSIC.1995.520704","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520704","url":null,"abstract":"We have proposed a new 1/4 Vcc bit-line swing architecture and related sense amplifier for 1 V 4 Gb DRAM and beyond. These schemes reduce power dissipation to 40% without degradation of the read-out signal and also improve device reliability.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129688983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 286 MHz 64-bit floating point multiplier with enhanced CG operation 286兆赫64位浮点乘法器与增强的CG操作
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520666
H. Makino, Hiroaki Suzuki, H. Morinaka, Y. Nakase, K. Mashiko, T. Sumi
{"title":"A 286 MHz 64-bit floating point multiplier with enhanced CG operation","authors":"H. Makino, Hiroaki Suzuki, H. Morinaka, Y. Nakase, K. Mashiko, T. Sumi","doi":"10.1109/VLSIC.1995.520666","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520666","url":null,"abstract":"High speed floating point (FP) multipliers are essential for high speed calculation systems because increasingly large numbers of FP multiplications must be carried out in various applications such as scientific calculation and computer graphics (CG). CG, in particular, requires enormous amount of FP multiplications to obtain high quality images required for multimedia systems. To realize high speed, the critical path delay must be minimized. In this paper, we discuss a method to shorten the delay time of the critical path. Then we present an FP multiplier design based on the method. A special function for CG is also implemented without increasing the critical path delay. Finally, we show the fabrication and test results of the FP multiplier.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128304770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Efficient charge recovery logic 高效电荷恢复逻辑
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520719
Yongsam Moon, D. Jeong
{"title":"Efficient charge recovery logic","authors":"Yongsam Moon, D. Jeong","doi":"10.1109/VLSIC.1995.520719","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520719","url":null,"abstract":"Efficient Charge Recovery Logic (ECRL) is proposed as a candidate for low-energy adiabatic logic. Power comparison with other logic circuits is performed on an inverter chain and a carry lookahead adder (CLA). ECRL CLA is designed as a pipelined structure for obtaining the same throughput as a conventional static CMOS CLA. Proposed logic shows 4-6 times power range with a practical loading and operation frequency range. Circuits are designed using 1.0 /spl mu/m CMOS technology with a reduced threshold voltage of 0.2 V.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128675280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Voltage-comparator-based measurement of equivalently sampled substrate noise waveform in mixed-signal integrated circuits 混合信号集成电路中等效采样衬底噪声波形的电压比较器测量
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520678
K. Makie-Fukuda, T. Anbo, T. Tsukada, T. Matsuura, M. Hotta
{"title":"Voltage-comparator-based measurement of equivalently sampled substrate noise waveform in mixed-signal integrated circuits","authors":"K. Makie-Fukuda, T. Anbo, T. Tsukada, T. Matsuura, M. Hotta","doi":"10.1109/VLSIC.1995.520678","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520678","url":null,"abstract":"A method is proposed for measuring substrate noise waveforms in mixed-signal integrated circuits. This method uses wideband chopper-type single-ended voltage comparators as on-chip noise detectors. By analyzing the equivalently sampled comparator outputs from synchronized operation, the noise voltages in auto-zero and compare modes can be separately detected and the noise waveforms can be reconstructed within 2-nsec accuracy. The measured results also explain the influence of noise coupling on analog circuits widely used in on-chip analog to digital converters.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127536009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 63
A MOSFET-only continuous-time 560 kHz tunable bandpass filter 一个仅mosfet的连续560khz可调谐带通滤波器
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520701
Qiuting Huang
{"title":"A MOSFET-only continuous-time 560 kHz tunable bandpass filter","authors":"Qiuting Huang","doi":"10.1109/VLSIC.1995.520701","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520701","url":null,"abstract":"A MOSFET-only filter is described which employs an amplifier-regulated cascode structure to realize both conductance and transconductance, while the required capacitors are realized by MOSFET gate capacitance. The filter configuration is such that both MOSFET capacitors and MOSFET resistors are always biased in the triode region, so that the only remaining nonlinearity is that caused by mobility degradation due to the normal field, which can be reduced by differential structures.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129999176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 16 bit low-power-consumption digital signal processor using a 80 MOPS redundant binary MAC 采用80 MOPS冗余二进制MAC的16位低功耗数字信号处理器
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520686
H. Kabuo, M. Okamoto, R. Tanaka, H. Yasoshima, S. Marui, M. Yamasaki, T. Sugimura, K. Ueda, T. Ishikawa, H. Suzuki, R. Asahi
{"title":"A 16 bit low-power-consumption digital signal processor using a 80 MOPS redundant binary MAC","authors":"H. Kabuo, M. Okamoto, R. Tanaka, H. Yasoshima, S. Marui, M. Yamasaki, T. Sugimura, K. Ueda, T. Ishikawa, H. Suzuki, R. Asahi","doi":"10.1109/VLSIC.1995.520686","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520686","url":null,"abstract":"This paper describes a 16b fixed point digital signal processor (DSP), especially a variable pipeline multiply-accumulate (MAC) unit using a redundant binary representation. This new MAC unit improves 9.8% in power consumption and 249b in operation speed at multiply and multiply-accumulate operation over a conventional MAC unit. This chip is fabricated with a 0.5 um double-metal-layer CMOS process and achieves 40 MIPS and 80 MOPS-peak performance.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122880784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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