用于1v 4gb DRAM的250mv位线摆振方案

Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI:10.1109/VLSIC.1995.520704

T. Inaba, D. Takashima, Y. Oowaki, T. Ozaki, S. Watanabe, K. Ohuchi

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引用次数: 2

摘要

我们提出了一种新的1/ 4vcc位线摆振结构和相关的感测放大器，适用于1v 4gb及以上的DRAM。这些方案在不降低读出信号的情况下将功耗降低到40%，并提高了设备的可靠性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 250 mV bit-line swing scheme for a 1 V 4 Gb DRAM

We have proposed a new 1/4 Vcc bit-line swing architecture and related sense amplifier for 1 V 4 Gb DRAM and beyond. These schemes reduce power dissipation to 40% without degradation of the read-out signal and also improve device reliability.

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Digest of Technical Papers., Symposium on VLSI Circuits.

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