采用80 MOPS冗余二进制MAC的16位低功耗数字信号处理器

Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI:10.1109/VLSIC.1995.520686

H. Kabuo, M. Okamoto, R. Tanaka, H. Yasoshima, S. Marui, M. Yamasaki, T. Sugimura, K. Ueda, T. Ishikawa, H. Suzuki, R. Asahi

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引用次数: 4

摘要

本文介绍了一种16b定点数字信号处理器(DSP)，特别是采用冗余二进制表示的可变流水线乘累加(MAC)单元。与传统的MAC单元相比，这种新的MAC单元在乘法和乘法累加运算时的功耗提高了9.8%，运算速度提高了249b。该芯片采用0.5 um双金属层CMOS工艺制造，峰值性能达到40 MIPS和80 mops。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 16 bit low-power-consumption digital signal processor using a 80 MOPS redundant binary MAC

This paper describes a 16b fixed point digital signal processor (DSP), especially a variable pipeline multiply-accumulate (MAC) unit using a redundant binary representation. This new MAC unit improves 9.8% in power consumption and 249b in operation speed at multiply and multiply-accumulate operation over a conventional MAC unit. This chip is fabricated with a 0.5 um double-metal-layer CMOS process and achieves 40 MIPS and 80 MOPS-peak performance.

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Digest of Technical Papers., Symposium on VLSI Circuits.

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