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Statistical electromigration budgeting for reliable design and verification in a 300-MHz microprocessor 300mhz微处理器可靠设计与验证的统计电迁移预算
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520712
J. Kitchin
{"title":"Statistical electromigration budgeting for reliable design and verification in a 300-MHz microprocessor","authors":"J. Kitchin","doi":"10.1109/VLSIC.1995.520712","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520712","url":null,"abstract":"Statistical Electromigration Budgeting (SEB) is a novel method for setting and verifying electromigration (EM) design requirements for VLSI interconnect. SEB exploits the statistical nature of EM reliability to selectively supersede fixed current density design rules for some interconnect, allowing increased chip performance while simultaneously quantifying chip-level EM reliability to directly assure design conformance to reliability requirements. The concept and method of SEB are introduced, and some results from its application in the design and verification of the Alpha 21164300 microprocessor are given.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130313157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
A 0.4 /spl mu/m 1.4 ns 32b dynamic adder using non-precharge multiplexers and reduced precharge voltage technique 采用非预充电复用器和降低预充电电压技术的0.4 /spl mu/m 1.4 ns 32b动态加法器
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520663
A. Inoue, Y. Kawabe, Y. Asada, S. Ando
{"title":"A 0.4 /spl mu/m 1.4 ns 32b dynamic adder using non-precharge multiplexers and reduced precharge voltage technique","authors":"A. Inoue, Y. Kawabe, Y. Asada, S. Ando","doi":"10.1109/VLSIC.1995.520663","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520663","url":null,"abstract":"This paper describes fast 32-bit dynamic adder using nonprecharge multiplexers and reduced precharge voltage technique. Design adopting novel multiplexers reduces transistor count, resulting in the reduction of total parasitic capacitance. Reduced precharge voltage makes the discharge time shorter. Experimental circuit has been fabricated using 0.4 /spl mu/m CMOS technology and we confirmed the delay of 1.4 ns at the supply voltage of 3.3 V at room temperature.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114782254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Active matrix LCDs: a clear, bright future 有源矩阵液晶:一个清晰、光明的未来
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520662
A. Lewis
{"title":"Active matrix LCDs: a clear, bright future","authors":"A. Lewis","doi":"10.1109/VLSIC.1995.520662","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520662","url":null,"abstract":"Active matrix liquid crystal displays (AMLCDs) dominate the high performance flat panel display market, and over the next few years AMLCDs will begin displacing CRTs as the most common display device. This paper reviews the technologies underlying AMLCDs, and examines the advances likely to occur in the future which will not only improve the image quality and power consumption of these displays, but open up completely new areas of application and markets.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122065217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A low noise 32 bit-wide 256 M synchronous DRAM with column-decoded I/O line 具有列解码I/O线的低噪声32位宽256m同步DRAM
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520711
Seungjin Lee, Kee-Woo Park, Chang-Ho Chung, Jin-Seung Son, Ki-Hong Park, Sanghoon Shin, Seok-Tae Kim, Jeong-Dong Han, H. Yoo, W. Min, K. Oh
{"title":"A low noise 32 bit-wide 256 M synchronous DRAM with column-decoded I/O line","authors":"Seungjin Lee, Kee-Woo Park, Chang-Ho Chung, Jin-Seung Son, Ki-Hong Park, Sanghoon Shin, Seok-Tae Kim, Jeong-Dong Han, H. Yoo, W. Min, K. Oh","doi":"10.1109/VLSIC.1995.520711","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520711","url":null,"abstract":"A 32 bit-wide 256 M synchronous DRAM (SDRAM) has been developed. The major design effort has been focused on minimizing the operating current at high clock frequencies to suppress power-line bouncing. The key techniques are split-bank architecture, multiplexed global address-bus with local column address counter, column-decoded data-line, and global data-bus architecture with reduced voltage swing. Simulation shows the reduction in the operating current at 200 MHz is up to 35% compared with a conventional scheme.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124286315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A single chip MPEG1 decoder 单片MPEG1解码器
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520687
K. Kawahara, T. Yamauchi, S. Okada
{"title":"A single chip MPEG1 decoder","authors":"K. Kawahara, T. Yamauchi, S. Okada","doi":"10.1109/VLSIC.1995.520687","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520687","url":null,"abstract":"A single chip MPEG1 decoder was developed. It contains MPEG1 video/audio/system decoders and also include a GD-ROM decoder for package media application. The outstanding feature of the chip is its high quality control of MPEG1 system such as buffer management and AV synchronization. The chip basically decodes a MPEG1 stream automatically without the support of an external microprocessor. The circuit was designed using dedicated hardwired logic resulting in a low cost and low power chip.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121544437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Cell-plate-line and bit-line complementarily sensed (CBCS) architecture for ultra low-power non-destructive DRAMs 超低功耗非破坏性dram的cell -板线和位线互补感测(CBCS)架构
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520694
T. Hamamoto, Y. Morooka, M. Asakura, H. Ozaki
{"title":"Cell-plate-line and bit-line complementarily sensed (CBCS) architecture for ultra low-power non-destructive DRAMs","authors":"T. Hamamoto, Y. Morooka, M. Asakura, H. Ozaki","doi":"10.1109/VLSIC.1995.520694","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520694","url":null,"abstract":"In order to develop very high density DRAMs, the reduction of memory-array current, accounting for over 80% of total chip current, must be given serious consideration. As the number of activated sense-amplifiers (SAs) increase, the amount of consumed charge on bit-lines (BLs) increases accordingly. This paper describes a novel circuit design, called Cell-Plate-Line and Bit-Line Complementarily Sensed (CBCS) Architecture. Only the selected SA of a whole array is activated, thereby reducing array read/write current to below 1% compared with conventional ones. Furthermore, refresh operation can easily be executed and the array refresh current is reduced to below 50% without loss of the read-out differential signal.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130309468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Driving source-line (DSL) cell architecture for sub-1-V high-speed low-power applications 用于sub- 1v高速低功耗应用的驱动源线(DSL)单元架构
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520671
H. Mizuno, T. Nagano
{"title":"Driving source-line (DSL) cell architecture for sub-1-V high-speed low-power applications","authors":"H. Mizuno, T. Nagano","doi":"10.1109/VLSIC.1995.520671","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520671","url":null,"abstract":"A novel SRAM cell architecture for sub-1-V high-speed operation is proposed without using either low-V/sub th/ MOSFETs or modifying the cell layout pattern. A source-line connected to the source terminals of driver MOSFETs is controlled to be negative and floating in the read- and write-cycles, respectively. The cell-access time is reduced to 1/4-1/2 at a supply voltage of 0.5-1.0 V. Limiting the bit-line swing reduced the writing power needed to charge the bit-lines to 1/10, and it realizes a faster write-recovery. The feasibility of low-power 100 MHz operation over a wide range of supply voltages is demonstrated.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133799481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 112
A post processing method for reducing substrate coupling in mixed-signal integrated circuits 一种用于减少混合信号集成电路中衬底耦合的后处理方法
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520679
P. Basedau, Qiuting Huang
{"title":"A post processing method for reducing substrate coupling in mixed-signal integrated circuits","authors":"P. Basedau, Qiuting Huang","doi":"10.1109/VLSIC.1995.520679","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520679","url":null,"abstract":"Due to the heavily doped substrate material in modern MOS technologies, digital interference couples to sensitive analog nodes much more easily than in technologies with p/sup -/ substrates. The guard ring method of isolating sensitive nodes is no longer as effective as before. In this contribution we investigate the isolation of analog circuits by etching a gap between analog and digital circuits from the back of the wafer. Experiments show that interference coupling 35 dB above noise floor is completely removed when a gap is etched around the analog circuit.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133846209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
An accurate quasi-saturation BJT model for very-high-frequency analog/digital applications 高精度准饱和BJT模型，适用于高频模拟/数字应用
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520715
T. Fuse, Y. Shuto, Y. Oowaki
{"title":"An accurate quasi-saturation BJT model for very-high-frequency analog/digital applications","authors":"T. Fuse, Y. Shuto, Y. Oowaki","doi":"10.1109/VLSIC.1995.520715","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520715","url":null,"abstract":"An accurate quasi-saturation BJT model is proposed for very-high-frequency analog and digital applications. In modern low-power analog and digital circuits, the BJT often operates in a low collector voltage and high collector current region. Under such a quasi-saturation condition, base and collector resistances have nonlinear characteristics and the base pushout phenomenon occurs. However, these phenomena are not taken into the conventional small-signal model accurately, so that the collector current, the small-signal input impedance, and the small-signal current gain are overestimated under the quasi-saturation condition. We have developed linearized base and collector resistance models and the physically based base pushout model for accurate circuit simulations.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122903258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 250-622 MHz deskew and jitter-suppressed clock buffer using a frequencyand delay-locked two-loop architecture 使用频率和延迟锁定双环架构的250-622 MHz桌位和抖动抑制时钟缓冲器
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520697
S. Tanoi, T. Tanabe, K. Tgkahashi, S. Miyamoto, M. Uesugi
{"title":"A 250-622 MHz deskew and jitter-suppressed clock buffer using a frequencyand delay-locked two-loop architecture","authors":"S. Tanoi, T. Tanabe, K. Tgkahashi, S. Miyamoto, M. Uesugi","doi":"10.1109/VLSIC.1995.520697","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520697","url":null,"abstract":"Recently, several delay-locked loop (DLL) circuits for on-chip clock supply have been reported. In this paper a new 2-loop circuit has been designed for on-chip clock-supply applications which require a quick pull-in, suppressed jitter in a wide operating frequency range. The design technologies included are: 1) A 2-loop architecture in which a frequency-locked loop (FLL) is provided separately from a DLL for quick pull-in over a wide frequency range; 2) A current-mode phase detector (CMPD) used in the DLL, which makes use of a flip-flop metastability for increasing the phase-difference detecting sensitivity.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121384387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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