Statistical electromigration budgeting for reliable design and verification in a 300-MHz microprocessor

Abstract

Statistical Electromigration Budgeting (SEB) is a novel method for setting and verifying electromigration (EM) design requirements for VLSI interconnect. SEB exploits the statistical nature of EM reliability to selectively supersede fixed current density design rules for some interconnect, allowing increased chip performance while simultaneously quantifying chip-level EM reliability to directly assure design conformance to reliability requirements. The concept and method of SEB are introduced, and some results from its application in the design and verification of the Alpha 21164300 microprocessor are given.