{"title":"单片MPEG1解码器","authors":"K. Kawahara, T. Yamauchi, S. Okada","doi":"10.1109/VLSIC.1995.520687","DOIUrl":null,"url":null,"abstract":"A single chip MPEG1 decoder was developed. It contains MPEG1 video/audio/system decoders and also include a GD-ROM decoder for package media application. The outstanding feature of the chip is its high quality control of MPEG1 system such as buffer management and AV synchronization. The chip basically decodes a MPEG1 stream automatically without the support of an external microprocessor. The circuit was designed using dedicated hardwired logic resulting in a low cost and low power chip.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"40 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A single chip MPEG1 decoder\",\"authors\":\"K. Kawahara, T. Yamauchi, S. Okada\",\"doi\":\"10.1109/VLSIC.1995.520687\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A single chip MPEG1 decoder was developed. It contains MPEG1 video/audio/system decoders and also include a GD-ROM decoder for package media application. The outstanding feature of the chip is its high quality control of MPEG1 system such as buffer management and AV synchronization. The chip basically decodes a MPEG1 stream automatically without the support of an external microprocessor. The circuit was designed using dedicated hardwired logic resulting in a low cost and low power chip.\",\"PeriodicalId\":256846,\"journal\":{\"name\":\"Digest of Technical Papers., Symposium on VLSI Circuits.\",\"volume\":\"40 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-06-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Technical Papers., Symposium on VLSI Circuits.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.1995.520687\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Technical Papers., Symposium on VLSI Circuits.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1995.520687","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A single chip MPEG1 decoder was developed. It contains MPEG1 video/audio/system decoders and also include a GD-ROM decoder for package media application. The outstanding feature of the chip is its high quality control of MPEG1 system such as buffer management and AV synchronization. The chip basically decodes a MPEG1 stream automatically without the support of an external microprocessor. The circuit was designed using dedicated hardwired logic resulting in a low cost and low power chip.
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