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Digest of Technical Papers., Symposium on VLSI Circuits.最新文献

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Integrating intelligence on silicon electronic systems. An inter-University cooperative research project for innovative process, device, circuit, and system technologies 集成硅电子系统的智能。校际合作研究项目，研究创新制程、装置、电路及系统技术
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520661
T. Ohmi
{"title":"Integrating intelligence on silicon electronic systems. An inter-University cooperative research project for innovative process, device, circuit, and system technologies","authors":"T. Ohmi","doi":"10.1109/VLSIC.1995.520661","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520661","url":null,"abstract":"An inter-university cooperative research project has been launched aiming at creating a new paradigm of computing hardware based on silicon technology. The binary multivalued-analog merged hardware computation based on four-terminal device with innovative architecture is the guiding principle for the development of an intelligent system. And most importantly, the research on the high accuracy processing and materials technology that substantialize the advanced system on a silicon chip is inseparably merged into the entire project.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126033807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A current direction sense technique for multi-port SRAMs 当前多端口sram的方向检测技术
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520670
Masanori Izumikawa, M. Yamashina
{"title":"A current direction sense technique for multi-port SRAMs","authors":"Masanori Izumikawa, M. Yamashina","doi":"10.1109/VLSIC.1995.520670","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520670","url":null,"abstract":"Single-end sense amplifiers which do not require a reference voltage would be most desirable for multi-port SRAMs. This paper describes a current-direction sense circuit which transforms current direction into a logic value. It operates 4 times faster than a CMOS inverter, and with it it is possible to produce single-end 200 MHz 64 Kb SRAMs whose total power consumption is nearly as low as that required for the memory cell currents alone in conventional SRAMs. Also presented is a write bit-line swing control circuit which uses a memory cell replica to reduce bit-line and word-line swing. When this circuit is applied to be used in a 200 MHz 64 Kb SRAM, it is possible to reduce by one-third the power consumption required for bit-line driving and pseudo-read cell current (0.25 /spl mu/m CMOS).","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129982482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
A CMOS limiting amplifier and signal-strength indicator 一个CMOS限制放大器和信号强度指示器
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520702
S. Khorram, A. Rofougaran, A. Abidi
{"title":"A CMOS limiting amplifier and signal-strength indicator","authors":"S. Khorram, A. Rofougaran, A. Abidi","doi":"10.1109/VLSIC.1995.520702","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520702","url":null,"abstract":"Although all commercially available monolithic log amps today are bipolar ICs, CMOS is equally well-suited to implement the successive-detection architecture. We report here on the design and performance of such a logarithmic amplifier, which is part of a monolithic all-CMOS spread-spectrum 900 MHz wireless transceiver. In the intended use, a received 160 kb/s binary-FSK signal is amplified at RF, directly downconverted to DC, and applied to the logarithmic amplifier after channel-select filtering. The amplifier provides two useful outputs. First, the limited output from the cascade of clipping amplifiers contains the data encoded as signal phase in the zero-crossings. Second, the circuit produces a logarithmic signal-strength measurement to an accuracy of 1 dB over a 80 dB dynamic range.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"18 20","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113973400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 50
A 1-V high-speed MTCMOS circuit scheme for power-down applications 一种用于断电应用的1v高速MTCMOS电路方案
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520717
S. Shigematsu, S. Mutoh, Y. Matsuya, J. Yamada
{"title":"A 1-V high-speed MTCMOS circuit scheme for power-down applications","authors":"S. Shigematsu, S. Mutoh, Y. Matsuya, J. Yamada","doi":"10.1109/VLSIC.1995.520717","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520717","url":null,"abstract":"A new MTCMOS concept is proposed for power-down applications. This concept realises a new circuit scheme to hold data during the power-down period in which the power is not supplied. Low-power, high-speed performance are achieved by separating the holding circuit from the critical path. A scan register has been developed based on this concept. Using this scheme for an LSI chip, 20-MHz operation at 1.0 V and only a few nA standby current was achieved with 0.5-/spl mu/m CMOS technology.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"249 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116190049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 84
SOI-DRAM circuit technologies for low power high speed multi-giga scale memories 用于低功耗高速千兆存储器的SOI-DRAM电路技术
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520706
S. Kuge, F. Morishita, T. Tsuruda, S. Tomishima, M. Tsukude, T. Yamagata, K. Arimoto
{"title":"SOI-DRAM circuit technologies for low power high speed multi-giga scale memories","authors":"S. Kuge, F. Morishita, T. Tsuruda, S. Tomishima, M. Tsukude, T. Yamagata, K. Arimoto","doi":"10.1109/VLSIC.1995.520706","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520706","url":null,"abstract":"New SOI-DRAM circuits were proposed and described. The body bias controlling technique, especially super body-synchronous sensing, is found to be suitable for low voltage operation. A new type of redundancy enables Icc2 reduction and promises high yield against the increasing standby current failure.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123553638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A 5V-only 16M flash memory using a contactless array of source-side injection cells 5v - 16M闪存，采用源侧注射单元的非接触式阵列
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520693
S. Tsao, J. Frayer, C.S. Pang, Y. Ma, K. Kwon, Y. Choi, D. Kim, J. Kim, J. Park
{"title":"A 5V-only 16M flash memory using a contactless array of source-side injection cells","authors":"S. Tsao, J. Frayer, C.S. Pang, Y. Ma, K. Kwon, Y. Choi, D. Kim, J. Kim, J. Park","doi":"10.1109/VLSIC.1995.520693","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520693","url":null,"abstract":"The source side injection technology coupled with a modified virtual ground contactless array architecture is effective in addressing high density FLASH requirements. We describe a single supply 16 Mbit chip developed in a 0.7 /spl mu/m triple-poly double metal process using a 3.36 /spl mu/m/sup 2/ cell. The design challenge is to implement all the necessary array interface circuitry while maintaining a high array-to-chip area efficiency. This implementation requires unique decoding circuitry on the bitlines and cell control gates.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125226245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 2.25 gbytes/s 1 Mbit smart cache SRAM 2.25 gb /s 1 Mbit智能缓存SRAM
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520667
J. Ku, S. Siu, M. Yazdani, Yolin Lih, Wei Lu, A. Desroches
{"title":"A 2.25 gbytes/s 1 Mbit smart cache SRAM","authors":"J. Ku, S. Siu, M. Yazdani, Yolin Lih, Wei Lu, A. Desroches","doi":"10.1109/VLSIC.1995.520667","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520667","url":null,"abstract":"The wide-word architecture is widely regionized as the next generation CPU architecture by most of the system vendors. This type of architecture requires high speed, high bandwidth second level cache memory to support it. Since the efficiency and the flexibility of the cache line transaction in between the CPU and the memory control unit would greatly affect the overall system performance, those important cache data transferring functions such as byte write, bypass, compare and swap capabilities have to be included in the second level cache to achieve the optimal performance. One of the project goals within HP wide-word program is to design a 16 K/spl times/72 synchronous, pipelined smart cache SRAM which is capable of sending out data at a rate of 2.25 Gbyte data per second.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117089397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 2.5-Gb/sec 15-mW BiCMOS clock recovery circuit 一个2.5 gb /秒的15mw BiCMOS时钟恢复电路
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520696
B. Raeavi, J. Sung
{"title":"A 2.5-Gb/sec 15-mW BiCMOS clock recovery circuit","authors":"B. Raeavi, J. Sung","doi":"10.1109/VLSIC.1995.520696","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520696","url":null,"abstract":"High-speed low-power clock recovery circuits find wide application in high-performance communication systems. This paper describes the design of a 2.5-Gb/sec 15-mW clock recovery circuit (CRC) fabricated in a 20-GHz 1-/spl mu/m BiCMOS technology. Employing a modified version of the \"quadricorrelator\" architecture, the circuit extracts the clock from a non-return-to-zero (NRZ) data sequence using both phase and frequency detection.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128876810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A low-power single-chip microprocessor with multiple page-size MMU for nomadic computing 一种低功耗单芯片微处理器，具有多页大小的MMU，用于游牧计算
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520684
S. Narita, K. Ishibashi, S. Tachibana, K. Norisue, Y. Shimazaki, J. Nishimoto, K. Uchiyama, T. Nakazawa, K. Hirose, I. Kudoh, R. Izawa, S. Matsui, S. Yoshioka, M. Yamamoto, I. Kawasaki
{"title":"A low-power single-chip microprocessor with multiple page-size MMU for nomadic computing","authors":"S. Narita, K. Ishibashi, S. Tachibana, K. Norisue, Y. Shimazaki, J. Nishimoto, K. Uchiyama, T. Nakazawa, K. Hirose, I. Kudoh, R. Izawa, S. Matsui, S. Yoshioka, M. Yamamoto, I. Kawasaki","doi":"10.1109/VLSIC.1995.520684","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520684","url":null,"abstract":"A low-power single-chip RISC microprocessor has been designed. It based on Hitachi's SH architecture with multiple page-size MMU. An automatic-power-save cache memory reduces the power dissipation at low frequencies, Two low-power modes and a module-stop function are software programmable for system power management. MMU supports 4 KB and 1 KB page-sizes by 4-way set-associative TLB. The chip using 0.5 um CMOS technology is fabricated, and achieves 60 Dhrystone MIPS and keeps 600 mW (max.), 60 MHz at worst condition.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127828884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Design aspects of 10 to 40 Gb/s digital and analog Si-bipolar ICs 设计10 ~ 40gb /s数字和模拟硅双极ic
Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI: 10.1109/VLSIC.1995.520682
H. Rein
{"title":"Design aspects of 10 to 40 Gb/s digital and analog Si-bipolar ICs","authors":"H. Rein","doi":"10.1109/VLSIC.1995.520682","DOIUrl":"https://doi.org/10.1109/VLSIC.1995.520682","url":null,"abstract":"In this paper design aspects are discussed which allow one to exhaust the high speed potential of advanced Si bipolar technologies. Starting from the most promising circuit concepts and an adequate resistance level, the transistor geometries must be optimized very carefully using advanced transistor models. It is shown how the bond inductances can be favorably used and how the (critical) on-chip wiring must be taken into account. An inexpensive mounting technique proved to be well suited up to 50 Gb/s. The suitability of the design aspects discussed is confirmed by measurements of ICs for 10 and 40 Gb/s optical-fiber links.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"22 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120908960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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