A 2.5-Gb/sec 15-mW BiCMOS clock recovery circuit

Abstract

High-speed low-power clock recovery circuits find wide application in high-performance communication systems. This paper describes the design of a 2.5-Gb/sec 15-mW clock recovery circuit (CRC) fabricated in a 20-GHz 1-/spl mu/m BiCMOS technology. Employing a modified version of the "quadricorrelator" architecture, the circuit extracts the clock from a non-return-to-zero (NRZ) data sequence using both phase and frequency detection.