A 2.25 gbytes/s 1 Mbit smart cache SRAM

Abstract

The wide-word architecture is widely regionized as the next generation CPU architecture by most of the system vendors. This type of architecture requires high speed, high bandwidth second level cache memory to support it. Since the efficiency and the flexibility of the cache line transaction in between the CPU and the memory control unit would greatly affect the overall system performance, those important cache data transferring functions such as byte write, bypass, compare and swap capabilities have to be included in the second level cache to achieve the optimal performance. One of the project goals within HP wide-word program is to design a 16 K/spl times/72 synchronous, pipelined smart cache SRAM which is capable of sending out data at a rate of 2.25 Gbyte data per second.