S. Narita, K. Ishibashi, S. Tachibana, K. Norisue, Y. Shimazaki, J. Nishimoto, K. Uchiyama, T. Nakazawa, K. Hirose, I. Kudoh, R. Izawa, S. Matsui, S. Yoshioka, M. Yamamoto, I. Kawasaki
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引用次数: 6
摘要
设计了一种低功耗的RISC单片机。它基于日立的SH体系结构，具有多个页面大小的MMU。自动省电缓存，降低低频功耗;两种低功耗模式和模块停止功能，通过软件编程实现系统电源管理。MMU通过4路集合关联TLB支持4kb和1kb的页面大小。该芯片采用0.5 um CMOS技术制造，达到60 Dhrystone MIPS，在最坏情况下保持600 mW(最大)，60 MHz。
A low-power single-chip microprocessor with multiple page-size MMU for nomadic computing
A low-power single-chip RISC microprocessor has been designed. It based on Hitachi's SH architecture with multiple page-size MMU. An automatic-power-save cache memory reduces the power dissipation at low frequencies, Two low-power modes and a module-stop function are software programmable for system power management. MMU supports 4 KB and 1 KB page-sizes by 4-way set-associative TLB. The chip using 0.5 um CMOS technology is fabricated, and achieves 60 Dhrystone MIPS and keeps 600 mW (max.), 60 MHz at worst condition.
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