{"title":"当前多端口sram的方向检测技术","authors":"Masanori Izumikawa, M. Yamashina","doi":"10.1109/VLSIC.1995.520670","DOIUrl":null,"url":null,"abstract":"Single-end sense amplifiers which do not require a reference voltage would be most desirable for multi-port SRAMs. This paper describes a current-direction sense circuit which transforms current direction into a logic value. It operates 4 times faster than a CMOS inverter, and with it it is possible to produce single-end 200 MHz 64 Kb SRAMs whose total power consumption is nearly as low as that required for the memory cell currents alone in conventional SRAMs. Also presented is a write bit-line swing control circuit which uses a memory cell replica to reduce bit-line and word-line swing. When this circuit is applied to be used in a 200 MHz 64 Kb SRAM, it is possible to reduce by one-third the power consumption required for bit-line driving and pseudo-read cell current (0.25 /spl mu/m CMOS).","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"38 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"29","resultStr":"{\"title\":\"A current direction sense technique for multi-port SRAMs\",\"authors\":\"Masanori Izumikawa, M. Yamashina\",\"doi\":\"10.1109/VLSIC.1995.520670\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Single-end sense amplifiers which do not require a reference voltage would be most desirable for multi-port SRAMs. This paper describes a current-direction sense circuit which transforms current direction into a logic value. It operates 4 times faster than a CMOS inverter, and with it it is possible to produce single-end 200 MHz 64 Kb SRAMs whose total power consumption is nearly as low as that required for the memory cell currents alone in conventional SRAMs. Also presented is a write bit-line swing control circuit which uses a memory cell replica to reduce bit-line and word-line swing. When this circuit is applied to be used in a 200 MHz 64 Kb SRAM, it is possible to reduce by one-third the power consumption required for bit-line driving and pseudo-read cell current (0.25 /spl mu/m CMOS).\",\"PeriodicalId\":256846,\"journal\":{\"name\":\"Digest of Technical Papers., Symposium on VLSI Circuits.\",\"volume\":\"38 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-06-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"29\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Technical Papers., Symposium on VLSI Circuits.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.1995.520670\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Technical Papers., Symposium on VLSI Circuits.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1995.520670","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A current direction sense technique for multi-port SRAMs
Single-end sense amplifiers which do not require a reference voltage would be most desirable for multi-port SRAMs. This paper describes a current-direction sense circuit which transforms current direction into a logic value. It operates 4 times faster than a CMOS inverter, and with it it is possible to produce single-end 200 MHz 64 Kb SRAMs whose total power consumption is nearly as low as that required for the memory cell currents alone in conventional SRAMs. Also presented is a write bit-line swing control circuit which uses a memory cell replica to reduce bit-line and word-line swing. When this circuit is applied to be used in a 200 MHz 64 Kb SRAM, it is possible to reduce by one-third the power consumption required for bit-line driving and pseudo-read cell current (0.25 /spl mu/m CMOS).