用于低功耗高速千兆存储器的SOI-DRAM电路技术

Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI:10.1109/VLSIC.1995.520706

S. Kuge, F. Morishita, T. Tsuruda, S. Tomishima, M. Tsukude, T. Yamagata, K. Arimoto

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引用次数: 20

摘要

提出并描述了新的SOI-DRAM电路。体偏控制技术，特别是超体同步传感技术，适用于低压工作。一种新型的冗余使Icc2减少，并承诺高产量，以应对不断增加的备用电流故障。

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SOI-DRAM circuit technologies for low power high speed multi-giga scale memories

New SOI-DRAM circuits were proposed and described. The body bias controlling technique, especially super body-synchronous sensing, is found to be suitable for low voltage operation. A new type of redundancy enables Icc2 reduction and promises high yield against the increasing standby current failure.

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Digest of Technical Papers., Symposium on VLSI Circuits.

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