一种用于断电应用的1v高速MTCMOS电路方案

Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI:10.1109/VLSIC.1995.520717

S. Shigematsu, S. Mutoh, Y. Matsuya, J. Yamada

{"title":"一种用于断电应用的1v高速MTCMOS电路方案","authors":"S. Shigematsu, S. Mutoh, Y. Matsuya, J. Yamada","doi":"10.1109/VLSIC.1995.520717","DOIUrl":null,"url":null,"abstract":"A new MTCMOS concept is proposed for power-down applications. This concept realises a new circuit scheme to hold data during the power-down period in which the power is not supplied. Low-power, high-speed performance are achieved by separating the holding circuit from the critical path. A scan register has been developed based on this concept. Using this scheme for an LSI chip, 20-MHz operation at 1.0 V and only a few nA standby current was achieved with 0.5-/spl mu/m CMOS technology.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"249 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"84","resultStr":"{\"title\":\"A 1-V high-speed MTCMOS circuit scheme for power-down applications\",\"authors\":\"S. Shigematsu, S. Mutoh, Y. Matsuya, J. Yamada\",\"doi\":\"10.1109/VLSIC.1995.520717\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new MTCMOS concept is proposed for power-down applications. This concept realises a new circuit scheme to hold data during the power-down period in which the power is not supplied. Low-power, high-speed performance are achieved by separating the holding circuit from the critical path. A scan register has been developed based on this concept. Using this scheme for an LSI chip, 20-MHz operation at 1.0 V and only a few nA standby current was achieved with 0.5-/spl mu/m CMOS technology.\",\"PeriodicalId\":256846,\"journal\":{\"name\":\"Digest of Technical Papers., Symposium on VLSI Circuits.\",\"volume\":\"249 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-06-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"84\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Technical Papers., Symposium on VLSI Circuits.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.1995.520717\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Technical Papers., Symposium on VLSI Circuits.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1995.520717","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 84

摘要

提出了一种新的MTCMOS概念，用于断电应用。这个概念实现了一种新的电路方案，可以在断电期间不供电时保存数据。通过将保持电路与关键路径分离，实现了低功耗、高速性能。基于这一概念，已开发出扫描寄存器。该方案应用于LSI芯片，采用0.5-/spl μ m CMOS技术，可在1.0 V下实现20 mhz的工作，待机电流仅为几nA。

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A 1-V high-speed MTCMOS circuit scheme for power-down applications

A new MTCMOS concept is proposed for power-down applications. This concept realises a new circuit scheme to hold data during the power-down period in which the power is not supplied. Low-power, high-speed performance are achieved by separating the holding circuit from the critical path. A scan register has been developed based on this concept. Using this scheme for an LSI chip, 20-MHz operation at 1.0 V and only a few nA standby current was achieved with 0.5-/spl mu/m CMOS technology.

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Digest of Technical Papers., Symposium on VLSI Circuits.

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