一个2.5 gb /秒的15mw BiCMOS时钟恢复电路

Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI:10.1109/VLSIC.1995.520696

B. Raeavi, J. Sung

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引用次数: 5

摘要

高速低功耗时钟恢复电路在高性能通信系统中有着广泛的应用。本文设计了一种采用20 ghz 1-/spl mu/m BiCMOS技术制作的2.5 gb /秒15 mw时钟恢复电路(CRC)。该电路采用改进版的“四相关器”架构，利用相位和频率检测从非归零(NRZ)数据序列中提取时钟。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 2.5-Gb/sec 15-mW BiCMOS clock recovery circuit

High-speed low-power clock recovery circuits find wide application in high-performance communication systems. This paper describes the design of a 2.5-Gb/sec 15-mW clock recovery circuit (CRC) fabricated in a 20-GHz 1-/spl mu/m BiCMOS technology. Employing a modified version of the "quadricorrelator" architecture, the circuit extracts the clock from a non-return-to-zero (NRZ) data sequence using both phase and frequency detection.

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Digest of Technical Papers., Symposium on VLSI Circuits.

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