A 250-622 MHz deskew and jitter-suppressed clock buffer using a frequencyand delay-locked two-loop architecture

Abstract

Recently, several delay-locked loop (DLL) circuits for on-chip clock supply have been reported. In this paper a new 2-loop circuit has been designed for on-chip clock-supply applications which require a quick pull-in, suppressed jitter in a wide operating frequency range. The design technologies included are: 1) A 2-loop architecture in which a frequency-locked loop (FLL) is provided separately from a DLL for quick pull-in over a wide frequency range; 2) A current-mode phase detector (CMPD) used in the DLL, which makes use of a flip-flop metastability for increasing the phase-difference detecting sensitivity.