Cell-plate-line and bit-line complementarily sensed (CBCS) architecture for ultra low-power non-destructive DRAMs

Abstract

In order to develop very high density DRAMs, the reduction of memory-array current, accounting for over 80% of total chip current, must be given serious consideration. As the number of activated sense-amplifiers (SAs) increase, the amount of consumed charge on bit-lines (BLs) increases accordingly. This paper describes a novel circuit design, called Cell-Plate-Line and Bit-Line Complementarily Sensed (CBCS) Architecture. Only the selected SA of a whole array is activated, thereby reducing array read/write current to below 1% compared with conventional ones. Furthermore, refresh operation can easily be executed and the array refresh current is reduced to below 50% without loss of the read-out differential signal.