A low noise 32 bit-wide 256 M synchronous DRAM with column-decoded I/O line

Abstract

A 32 bit-wide 256 M synchronous DRAM (SDRAM) has been developed. The major design effort has been focused on minimizing the operating current at high clock frequencies to suppress power-line bouncing. The key techniques are split-bank architecture, multiplexed global address-bus with local column address counter, column-decoded data-line, and global data-bus architecture with reduced voltage swing. Simulation shows the reduction in the operating current at 200 MHz is up to 35% compared with a conventional scheme.