A 16 bit low-power-consumption digital signal processor using a 80 MOPS redundant binary MAC

Abstract

This paper describes a 16b fixed point digital signal processor (DSP), especially a variable pipeline multiply-accumulate (MAC) unit using a redundant binary representation. This new MAC unit improves 9.8% in power consumption and 249b in operation speed at multiply and multiply-accumulate operation over a conventional MAC unit. This chip is fabricated with a 0.5 um double-metal-layer CMOS process and achieves 40 MIPS and 80 MOPS-peak performance.