{"title":"100分接FIR/IIR模拟线性相位低通滤波器","authors":"Qiuting Huang, P. Maguire, T. Burger","doi":"10.1109/VLSIC.1995.520700","DOIUrl":null,"url":null,"abstract":"A 5 kHz linear-phase lowpass filter is implemented in a 2-/spl mu/m BiCMOS technology as a combination of a sigma-delta front-end, a digital shift register, an SC summer circuit of 50 input capacitors and an SC biquad running at a 1 MHz clock. The measured group delay variation in the passband is less than 1 /spl mu/s and the measured THD is -80 dB for an input sine wave amplitude of 0.7 V at 1 kHz.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A 100 tap FIR/IIR analog linear-phase lowpass filter\",\"authors\":\"Qiuting Huang, P. Maguire, T. Burger\",\"doi\":\"10.1109/VLSIC.1995.520700\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 5 kHz linear-phase lowpass filter is implemented in a 2-/spl mu/m BiCMOS technology as a combination of a sigma-delta front-end, a digital shift register, an SC summer circuit of 50 input capacitors and an SC biquad running at a 1 MHz clock. The measured group delay variation in the passband is less than 1 /spl mu/s and the measured THD is -80 dB for an input sine wave amplitude of 0.7 V at 1 kHz.\",\"PeriodicalId\":256846,\"journal\":{\"name\":\"Digest of Technical Papers., Symposium on VLSI Circuits.\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-06-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Technical Papers., Symposium on VLSI Circuits.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.1995.520700\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Technical Papers., Symposium on VLSI Circuits.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1995.520700","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 100 tap FIR/IIR analog linear-phase lowpass filter
A 5 kHz linear-phase lowpass filter is implemented in a 2-/spl mu/m BiCMOS technology as a combination of a sigma-delta front-end, a digital shift register, an SC summer circuit of 50 input capacitors and an SC biquad running at a 1 MHz clock. The measured group delay variation in the passband is less than 1 /spl mu/s and the measured THD is -80 dB for an input sine wave amplitude of 0.7 V at 1 kHz.