gb /s lsis电流镜像控制逻辑(CMCL)的低功耗双极电路

Digest of Technical Papers., Symposium on VLSI Circuits. Pub Date : 1995-06-08 DOI:10.1109/VLSIC.1995.520718

K. Kishine, H. Ichino

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引用次数: 5

摘要

提出了一种用于Gbit/s lsi的低功耗双极电路——电流镜像控制逻辑(CMCL)。为了降低电源电压，用电流镜像电路代替ECL串联栅极电路的低差分对。该CMCL电路可在-2.0 V的供电电压下实现3.1 gbit /s (D-F/F)和4.3 ghz (T-F/F)的工作，功耗仅为1.8 mW/(F/F)。

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A low-power bipolar circuit for Gbit/s LSIs-current mirror control logic (CMCL)

A low-power bipolar circuit for Gbit/s LSIs, Current Mirror Control Logic (CMCL), is proposed. To reduce supply voltage, the lower differential pairs of ECL series-gate circuits are replaced by current mirror circuits. This CMCL circuit achieves 3.1-Gbit/s (D-F/F) and 4.3-GHz (T-F/F) operation with a power supply voltage of -2.0 V and power dissipation of only 1.8 mW/(F/F).

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Digest of Technical Papers., Symposium on VLSI Circuits.

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