{"title":"用于神经网络的并行处理器","authors":"P. Lee, A. Sartori, G. Tecchiolli, A. Zorat","doi":"10.1109/VLSIC.1995.520695","DOIUrl":null,"url":null,"abstract":"A deeply-pipelined digital parallel processor for the implementation of Multi-Layer Perceptrons is presented. It employs high-speed limited-precision integer arithmetic and allows good recognition performance in combination with a novel training algorithm. Internal dynamic RAM is provided for storage of the weights. The chip achieves a performance of 600 million multiply-and-accumulate operations per second and requires a silicon area of 70 mm/sup 2/ in a 1.2-/spl mu/m CMOS technology.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A parallel processor for neural networks\",\"authors\":\"P. Lee, A. Sartori, G. Tecchiolli, A. Zorat\",\"doi\":\"10.1109/VLSIC.1995.520695\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A deeply-pipelined digital parallel processor for the implementation of Multi-Layer Perceptrons is presented. It employs high-speed limited-precision integer arithmetic and allows good recognition performance in combination with a novel training algorithm. Internal dynamic RAM is provided for storage of the weights. The chip achieves a performance of 600 million multiply-and-accumulate operations per second and requires a silicon area of 70 mm/sup 2/ in a 1.2-/spl mu/m CMOS technology.\",\"PeriodicalId\":256846,\"journal\":{\"name\":\"Digest of Technical Papers., Symposium on VLSI Circuits.\",\"volume\":\"25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-06-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Technical Papers., Symposium on VLSI Circuits.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.1995.520695\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Technical Papers., Symposium on VLSI Circuits.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1995.520695","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A deeply-pipelined digital parallel processor for the implementation of Multi-Layer Perceptrons is presented. It employs high-speed limited-precision integer arithmetic and allows good recognition performance in combination with a novel training algorithm. Internal dynamic RAM is provided for storage of the weights. The chip achieves a performance of 600 million multiply-and-accumulate operations per second and requires a silicon area of 70 mm/sup 2/ in a 1.2-/spl mu/m CMOS technology.
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