Y. Watanabe, H. Wong, T. Kirihata, D. Kato, J. DeBrosse, T. Hara, M. Yoshida, H. Mukai, K. Quader, T. Nagai, P. Poechmueller, K. Pfefferl, M. Wordeman, S. Fujii
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The growing market for high performance PCs has created a demand for a new generation of DRAMs with wide bit organization. A wider I/O DRAM is necessary to provide a sufficiently small granularity for the memory system. Hierarchical data-line architectures which transfer many bits over the memory array could potentially be used to provide a wide I/O. However, even using these schemes, chip size must expand to accommodate additional devices and wiring as the I/O width increases. This paper describes a chip architecture which minimizes the die size of wide I/O DRAMs and its application to a 256 Mb DRAM with X32 organization.
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