Pass transistor based gate array architecture

Abstract

This paper describes a completely new gate array architecture that fully exploits inherent advantages of pass transistor logic which a conventional architecture can not. In implementing SRAMs, our gate array achieves a 1.5 times higher density than a conventional gate array due to its different size transistors in the basic cell. An 8/spl times/8 b multiplier designed with this gate array using 0.4-/spl mu/m CMOS process achieves a multiplication time of 12.7 ns and dissipates 480 /spl mu/W with the supply voltage of 1.2 V. A 1.2 V 9 ns 1 kb SRAM was also designed with the same gate array.