A 286 mm/sup 2/ 256 Mb DRAM with X32 both-ends DQ

Abstract

The growing market for high performance PCs has created a demand for a new generation of DRAMs with wide bit organization. A wider I/O DRAM is necessary to provide a sufficiently small granularity for the memory system. Hierarchical data-line architectures which transfer many bits over the memory array could potentially be used to provide a wide I/O. However, even using these schemes, chip size must expand to accommodate additional devices and wiring as the I/O width increases. This paper describes a chip architecture which minimizes the die size of wide I/O DRAMs and its application to a 256 Mb DRAM with X32 organization.