Tomofumi lima, M. Mizuno, T. Horiuchi, M. Yamashina
{"title":"用于亚四分之一微米ULSI电阻互连信号的抗电容耦合、瞬态灵敏加速器","authors":"Tomofumi lima, M. Mizuno, T. Horiuchi, M. Yamashina","doi":"10.1109/VLSIC.1995.520674","DOIUrl":null,"url":null,"abstract":"We have developed a new circuit scheme that reduces the delay time caused by large interconnection resistances. Also, this circuit immunizes cross talk caused at scaled interconnections of sub-quarter micron ULSIs. The reduction of the delay time is 60% and output fluctuation is improved to negligibly small magnitude. The proposed circuit can be applied to bi-directional signal communication without adding further hardware and is extremely useful for sub-quarter micron ULSIs with scaled resistive interconnections.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"74 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"28","resultStr":"{\"title\":\"Capacitance coupling immune, transient sensitive accelerator for resistive interconnection signals of sub-quarter micron ULSI\",\"authors\":\"Tomofumi lima, M. Mizuno, T. Horiuchi, M. Yamashina\",\"doi\":\"10.1109/VLSIC.1995.520674\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We have developed a new circuit scheme that reduces the delay time caused by large interconnection resistances. Also, this circuit immunizes cross talk caused at scaled interconnections of sub-quarter micron ULSIs. The reduction of the delay time is 60% and output fluctuation is improved to negligibly small magnitude. The proposed circuit can be applied to bi-directional signal communication without adding further hardware and is extremely useful for sub-quarter micron ULSIs with scaled resistive interconnections.\",\"PeriodicalId\":256846,\"journal\":{\"name\":\"Digest of Technical Papers., Symposium on VLSI Circuits.\",\"volume\":\"74 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-06-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"28\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Technical Papers., Symposium on VLSI Circuits.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.1995.520674\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Technical Papers., Symposium on VLSI Circuits.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1995.520674","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Capacitance coupling immune, transient sensitive accelerator for resistive interconnection signals of sub-quarter micron ULSI
We have developed a new circuit scheme that reduces the delay time caused by large interconnection resistances. Also, this circuit immunizes cross talk caused at scaled interconnections of sub-quarter micron ULSIs. The reduction of the delay time is 60% and output fluctuation is improved to negligibly small magnitude. The proposed circuit can be applied to bi-directional signal communication without adding further hardware and is extremely useful for sub-quarter micron ULSIs with scaled resistive interconnections.
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