Fault-tolerant designs for 256 Mb DRAM

Abstract

Conventional redundancy architecture employs a repair region in each block, and therefore has disadvantages: (1) each block must have at least one (preferably two) redundant row and column, increasing design space; (2) grouped or clustered fails are difficult to repair; (3) a cross fail (WL/BL short-circuit) increases the stand-by current, causing a standby fail. Fault-tolerant designs were developed for a 256 Mb DRAM to overcome these problems by means of a redundancy block, interchangeable Master DQ's (MDQ's), and a current limiter.