T. Kirihata, Y. Watanabe, H. Wong, J. DeBrosse, M. Yoshida, D. Kato, S. Fujii, M. Wordeman, P. Poechmueller, Stephen A. Parke, Y. Asao
{"title":"256 Mb DRAM的容错设计","authors":"T. Kirihata, Y. Watanabe, H. Wong, J. DeBrosse, M. Yoshida, D. Kato, S. Fujii, M. Wordeman, P. Poechmueller, Stephen A. Parke, Y. Asao","doi":"10.1109/VLSIC.1995.520708","DOIUrl":null,"url":null,"abstract":"Conventional redundancy architecture employs a repair region in each block, and therefore has disadvantages: (1) each block must have at least one (preferably two) redundant row and column, increasing design space; (2) grouped or clustered fails are difficult to repair; (3) a cross fail (WL/BL short-circuit) increases the stand-by current, causing a standby fail. Fault-tolerant designs were developed for a 256 Mb DRAM to overcome these problems by means of a redundancy block, interchangeable Master DQ's (MDQ's), and a current limiter.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"36","resultStr":"{\"title\":\"Fault-tolerant designs for 256 Mb DRAM\",\"authors\":\"T. Kirihata, Y. Watanabe, H. Wong, J. DeBrosse, M. Yoshida, D. Kato, S. Fujii, M. Wordeman, P. Poechmueller, Stephen A. Parke, Y. Asao\",\"doi\":\"10.1109/VLSIC.1995.520708\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Conventional redundancy architecture employs a repair region in each block, and therefore has disadvantages: (1) each block must have at least one (preferably two) redundant row and column, increasing design space; (2) grouped or clustered fails are difficult to repair; (3) a cross fail (WL/BL short-circuit) increases the stand-by current, causing a standby fail. Fault-tolerant designs were developed for a 256 Mb DRAM to overcome these problems by means of a redundancy block, interchangeable Master DQ's (MDQ's), and a current limiter.\",\"PeriodicalId\":256846,\"journal\":{\"name\":\"Digest of Technical Papers., Symposium on VLSI Circuits.\",\"volume\":\"25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-06-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"36\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Technical Papers., Symposium on VLSI Circuits.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.1995.520708\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Technical Papers., Symposium on VLSI Circuits.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1995.520708","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Conventional redundancy architecture employs a repair region in each block, and therefore has disadvantages: (1) each block must have at least one (preferably two) redundant row and column, increasing design space; (2) grouped or clustered fails are difficult to repair; (3) a cross fail (WL/BL short-circuit) increases the stand-by current, causing a standby fail. Fault-tolerant designs were developed for a 256 Mb DRAM to overcome these problems by means of a redundancy block, interchangeable Master DQ's (MDQ's), and a current limiter.
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