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2008 IEEE Radio Frequency Integrated Circuits Symposium最新文献

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A RF CMOS amplifier with optimized gain, noise, linearity and return losses for UWB applications 一种射频CMOS放大器，具有优化的增益，噪声，线性度和回波损耗，用于超宽带应用
2008 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2008-07-15 DOI: 10.1109/RFIC.2008.4561487
G. D. Nguyen, K. Cimino, Milton Feng
{"title":"A RF CMOS amplifier with optimized gain, noise, linearity and return losses for UWB applications","authors":"G. D. Nguyen, K. Cimino, Milton Feng","doi":"10.1109/RFIC.2008.4561487","DOIUrl":"https://doi.org/10.1109/RFIC.2008.4561487","url":null,"abstract":"Trade-off between noise figure (NF) and input return loss (RL or |S11|) imposes a fundamental limitation on the design of low noise amplifiers (LNA) for ultra-wideband (UWB) applications. A graph-based approach using Smith Chart to achieve optimum values for both NF and input RL over the desired LNA bandwidth is presented. The proposed method and device optimization technique are systematically incorporated to enhance the overall LNA performance in terms of gain, noise, linearity, and power consumption. An UWB LNA prototype is implemented in a 0.13 mum CMOS process to demonstrate the use of this methodology. It shows a gain of 11.3 dB, a NF of 3.9-4.6 dB, and an IIP3 of 3.2-5 dBm over a -3 dB bandwidth of 2.2-9 GHz while consuming 30 mW from a 1.2 V DC supply.","PeriodicalId":253375,"journal":{"name":"2008 IEEE Radio Frequency Integrated Circuits Symposium","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114532640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
A direct conversion 4.9GHz to 5.925GHz OFDM receiver with Matched Non-Integer Quadrature LO 一种直接转换4.9GHz到5.925GHz的OFDM接收机，具有匹配的非整数正交LO
2008 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2008-07-15 DOI: 10.1109/RFIC.2008.4561506
N. Madan, A. Burstein, J. Park, K. Phillips, J. Feigin
{"title":"A direct conversion 4.9GHz to 5.925GHz OFDM receiver with Matched Non-Integer Quadrature LO","authors":"N. Madan, A. Burstein, J. Park, K. Phillips, J. Feigin","doi":"10.1109/RFIC.2008.4561506","DOIUrl":"https://doi.org/10.1109/RFIC.2008.4561506","url":null,"abstract":"A direct conversion 4.9 GHz to 5.925 GHz OFDM receiver IC with non-integer matched quadrature LO that supports channel bandwidths from 1 MHz to 28 MHz is manufactured on Jazz 0.35 mum BiCMOS process. This chip has a noise figure less than 6 dB and Input P1 dB of greater than -14 dBm at maximum gain. The I/Q gain mismatch is less than 0.15 dB and phase error is less than 3degree without any calibration during manufacturing or feedback from baseband.","PeriodicalId":253375,"journal":{"name":"2008 IEEE Radio Frequency Integrated Circuits Symposium","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114978332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A high-linearity, LC-Tuned, 24-GHz T/R switch in 90-nm CMOS 90nm CMOS高线性，lc调谐，24ghz T/R开关
2008 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2008-07-15 DOI: 10.1109/RFIC.2008.4561456
Piljae Park, Dong-Hun Shin, J. Pekarik, M. Rodwell, C. Yue
{"title":"A high-linearity, LC-Tuned, 24-GHz T/R switch in 90-nm CMOS","authors":"Piljae Park, Dong-Hun Shin, J. Pekarik, M. Rodwell, C. Yue","doi":"10.1109/RFIC.2008.4561456","DOIUrl":"https://doi.org/10.1109/RFIC.2008.4561456","url":null,"abstract":"This paper presents an LC-tuned, 24-GHz single-pole double-throw (SPDT) transmit/receive (T/R) switch implemented in 90-nm CMOS. The design focuses on the techniques to increase the power handling capability in the transmit (Tx) mode under 1.2-V operation. The switch achieves a measured P-1dB of 28.7 dBm, which represents the highest linearity, reported to date, for CMOS millimeter-wave T/R switches. The transmit and receive (Rx) branches employ different switch topologies to minimize the power leakage into the Rx path during Tx mode, and hence improve the linearity. To accommodate large signal swing, AC floating bias is applied using large bias resistors to all terminals of the switch devices. Triple-well devices are utilized to effectively float the substrate terminals. The switch uses a single 1.2-V digital control signal for T/R mode selection and for source/drain bias. The measured insertion loss is 3.5 dB and return loss is better than -10 dB at 24 GHz.","PeriodicalId":253375,"journal":{"name":"2008 IEEE Radio Frequency Integrated Circuits Symposium","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117231441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A 1.6-to-3.2/4.8 GHz dual-modulus injection-locked frequency multiplier in 0.18μm digital CMOS 基于0.18μm CMOS的1.6 ~ 3.2/4.8 GHz双模注入锁定倍频器
2008 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2008-07-15 DOI: 10.1109/RFIC.2008.4561469
Lin Zhang, D. Karasiewicz, B. Cifctioglu, Hui Wu
{"title":"A 1.6-to-3.2/4.8 GHz dual-modulus injection-locked frequency multiplier in 0.18μm digital CMOS","authors":"Lin Zhang, D. Karasiewicz, B. Cifctioglu, Hui Wu","doi":"10.1109/RFIC.2008.4561469","DOIUrl":"https://doi.org/10.1109/RFIC.2008.4561469","url":null,"abstract":"This paper proposes a variable-modulus injection-locked frequency multiplier for better harmonic suppression. It is more suitable for fully-integrated implementation using low-Q on-chip inductors in digital CMOS than conventional approaches. A prototype dual-modulus frequency doubler/tripler with 1.6 GHz input and 3.2 GHz/4.8 GHz output is implemented in a 0.18 mum standard digital CMOS. At 5% locking range, the doubler mode achieves fundamental suppression of 42 dB with 2.2 mW power consumption from 1 V supply; while the tripler mode achieves 40 dB suppression at the fundamental and 32 dB at the second harmonic, with 3.7 mWpower consumption from 1 V supply. Good phase noise performance is achieved for both doubler and tripler modes.","PeriodicalId":253375,"journal":{"name":"2008 IEEE Radio Frequency Integrated Circuits Symposium","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126161035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A high performance 2-GHz direct-conversion front end with single-ended RF input in 0.13 um CMOS 高性能2ghz直接转换前端，单端RF输入采用0.13 um CMOS
2008 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2008-07-15 DOI: 10.1109/RFIC.2008.4561449
Yiping Feng, Gaku Takemura, S. Kawaguchi, P. Kinget
{"title":"A high performance 2-GHz direct-conversion front end with single-ended RF input in 0.13 um CMOS","authors":"Yiping Feng, Gaku Takemura, S. Kawaguchi, P. Kinget","doi":"10.1109/RFIC.2008.4561449","DOIUrl":"https://doi.org/10.1109/RFIC.2008.4561449","url":null,"abstract":"This paper describes a 2.1-GHz CMOS front-end with a single-ended low noise amplifier (LNA) and a double balanced, current-driven passive mixer. The LNA features an on-chip transformer load to perform single-ended to differential conversion. Implemented in a 0.13 um CMOS process, it achieves 30 dB conversion gain, a low noise figure of 3.1 dB, a 40 kHz 1/f noise corner, an in-band IIP3 of -12 dBm and IIP2 better than 39 dBm, while consuming only 12 mW from a 1.5 V power supply.","PeriodicalId":253375,"journal":{"name":"2008 IEEE Radio Frequency Integrated Circuits Symposium","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124686295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A novel wide-band envelope detector 一种新型宽带包络探测器
2008 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2008-07-15 DOI: 10.1109/RFIC.2008.4561422
Yanping Zhou, Guochi Huang, Sangwook Nam, Byung-sung Kim
{"title":"A novel wide-band envelope detector","authors":"Yanping Zhou, Guochi Huang, Sangwook Nam, Byung-sung Kim","doi":"10.1109/RFIC.2008.4561422","DOIUrl":"https://doi.org/10.1109/RFIC.2008.4561422","url":null,"abstract":"In this paper, we present a novel wide-band envelope detector comprising a fully-differential operational transconductance amplifier (OTA), a full-wave rectifier and a peak detector. To enhance the frequency performance of the envelop detector, we utilize a gyrator-C active inductor load in the OTA for wider bandwidth. Additionally, it is shown that the high-speed rectifier of the envelope detector requires high bias current instead of the sub-threshold bias condition. The experimental results show that the proposed envelope detector can work from 100-Hz to 1.6-GHz with an input dynamic range of 50-dB at 100-Hz and 40-dB at 1.6-GHz, respectively. The envelope detector was fabricated on the TSMC 0.18-um CMOS process with an active area of 0.652 mm2.","PeriodicalId":253375,"journal":{"name":"2008 IEEE Radio Frequency Integrated Circuits Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129849392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
A GSM/EDGE transmitter in 0.13-μm CMOS using offset phase locked loop and direct conversion architecture 采用偏置锁相环和直接转换结构的0.13 μm CMOS GSM/EDGE发射机
2008 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2008-07-15 DOI: 10.1109/RFIC.2008.4561504
S.F. Chen, Y.B. Lee, B. Tzeng, C.C. Tang, C. Chiu, R. Yu, O. Lin, L. Ke, C.P. Wu, C.W. Yeh, P.Y. Chen, G. Dehng
{"title":"A GSM/EDGE transmitter in 0.13-μm CMOS using offset phase locked loop and direct conversion architecture","authors":"S.F. Chen, Y.B. Lee, B. Tzeng, C.C. Tang, C. Chiu, R. Yu, O. Lin, L. Ke, C.P. Wu, C.W. Yeh, P.Y. Chen, G. Dehng","doi":"10.1109/RFIC.2008.4561504","DOIUrl":"https://doi.org/10.1109/RFIC.2008.4561504","url":null,"abstract":"A GSM/EDGE transmitter implemented in 0.13-mum CMOS using offset phase locked loop and direct conversion architecture is presented. The transmitter consists of a DCT, an OPLL with a TXVCO, a fractional-N synthesizer with a RFVCO and LDO regulators. The transmitter delivers 1.5 dBm output power with 1.2deg rms phase error and the modulation spectrum at 400 kHz offset is better than -62 dBc in high band GSM mode. In high band EDGE mode, it has maximum 4 dBm output power with 0.5 dB gain step per bit for 36 dB dynamic range and 2% rms error vector magnitude. The current consumption of high band is 171 mA at GSM mode and 169 mA at EDGE mode under proper output power level for PA. This chip is housed in a 56-pin QFN package.","PeriodicalId":253375,"journal":{"name":"2008 IEEE Radio Frequency Integrated Circuits Symposium","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128158446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A tapered cascaded multi-stage distributed amplifier with 370GHz GBW in 90nm CMOS 90nm CMOS中370GHz GBW的锥形级联多级分布式放大器
2008 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2008-07-15 DOI: 10.1109/RFIC.2008.4561385
A. Arbabian, A. Niknejad
{"title":"A tapered cascaded multi-stage distributed amplifier with 370GHz GBW in 90nm CMOS","authors":"A. Arbabian, A. Niknejad","doi":"10.1109/RFIC.2008.4561385","DOIUrl":"https://doi.org/10.1109/RFIC.2008.4561385","url":null,"abstract":"A tapered cascaded multi-stage distributed amplifier (T-CMSDA) has been designed and fabricated in a 90 nm digital CMOS process. The amplifier achieves a 3-dB bandwidth of 73.5 GHz with a pass-band gain of 14 dB. This results in a gain-bandwidth (GBW) product of 370 GHz. The realized zero-dB BW is 83.5 GHz and the input and output matchings stay better than -9 dB up to 77 and 94 GHz, respectively. The chip consumes an area of 1.5 mm by 1.15 mm while drawing 70 mA from a 1.2 V supply.","PeriodicalId":253375,"journal":{"name":"2008 IEEE Radio Frequency Integrated Circuits Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129932202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
A BiCMOS voltage controlled oscillator and frequency doubler for K-band applications 用于k波段应用的BiCMOS压控振荡器和倍频器
2008 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2008-07-15 DOI: 10.1109/RFIC.2008.4561494
T. Copani, B. Bakkaloglu, S. Kiaei
{"title":"A BiCMOS voltage controlled oscillator and frequency doubler for K-band applications","authors":"T. Copani, B. Bakkaloglu, S. Kiaei","doi":"10.1109/RFIC.2008.4561494","DOIUrl":"https://doi.org/10.1109/RFIC.2008.4561494","url":null,"abstract":"A mm-wave voltage controlled oscillator and frequency doubler for 18-GHz applications are presented. A 9-GHz voltage controlled oscillator is implemented by using a double LC-tank resonator to improve loaded Q at high frequencies. Inductive coupling is exploited to design an 18-GHz frequency doubler, which improves spurious rejection and immunity to supply noise. The prototype is implemented in a SiGe BiCMOS process and performs a FOM of -183 dBc/Hz at 19 GHz.","PeriodicalId":253375,"journal":{"name":"2008 IEEE Radio Frequency Integrated Circuits Symposium","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131086892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 6-to-18 GHz tunable concurrent dual-band receiver front end for scalable phased arrays in 130nm CMOS 一种用于可扩展相控阵的6 ~ 18 GHz可调谐并发双频接收器前端
2008 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2008-07-15 DOI: 10.1109/RFIC.2008.4561450
Yu-Jiu Wang, S. Jeon, A. Babakhani, A. Hajimiri
{"title":"A 6-to-18 GHz tunable concurrent dual-band receiver front end for scalable phased arrays in 130nm CMOS","authors":"Yu-Jiu Wang, S. Jeon, A. Babakhani, A. Hajimiri","doi":"10.1109/RFIC.2008.4561450","DOIUrl":"https://doi.org/10.1109/RFIC.2008.4561450","url":null,"abstract":"This paper presents a study and design of tunable concurrent dual-band receiver. Different system architectures and building blocks have been compared and analyzed. A tunable concurrent dual-band receiver front end has then been fabricated and characterized. It operates across a tri-tave 6-18 GHz bandwidth with a nominal 17-25 dB conversion gain, worst-case -15 dBm IIP3, and worst-case -24.5 dBm ICP 1 dB.","PeriodicalId":253375,"journal":{"name":"2008 IEEE Radio Frequency Integrated Circuits Symposium","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132965278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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