S.F. Chen, Y.B. Lee, B. Tzeng, C.C. Tang, C. Chiu, R. Yu, O. Lin, L. Ke, C.P. Wu, C.W. Yeh, P.Y. Chen, G. Dehng
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引用次数: 2
摘要
提出了一种采用偏置锁相环和直接转换结构在0.13 μ m CMOS上实现的GSM/EDGE发射机。发射机由DCT、带TXVCO的OPLL、带RFVCO的分数n合成器和LDO调节器组成。发射机的输出功率为1.5 dBm，相位误差为1.2°rms，在400 kHz偏置下的调制频谱优于高频段GSM模式下的-62 dBc。在高频段EDGE模式下，它的最大输出功率为4 dBm，每比特增益为0.5 dB，动态范围为36 dB，有效值误差为2%。在适当的PA输出功率水平下，GSM模式下高频段的电流消耗为171毫安，EDGE模式下为169毫安。该芯片采用56针QFN封装。
A GSM/EDGE transmitter in 0.13-μm CMOS using offset phase locked loop and direct conversion architecture
A GSM/EDGE transmitter implemented in 0.13-mum CMOS using offset phase locked loop and direct conversion architecture is presented. The transmitter consists of a DCT, an OPLL with a TXVCO, a fractional-N synthesizer with a RFVCO and LDO regulators. The transmitter delivers 1.5 dBm output power with 1.2deg rms phase error and the modulation spectrum at 400 kHz offset is better than -62 dBc in high band GSM mode. In high band EDGE mode, it has maximum 4 dBm output power with 0.5 dB gain step per bit for 36 dB dynamic range and 2% rms error vector magnitude. The current consumption of high band is 171 mA at GSM mode and 169 mA at EDGE mode under proper output power level for PA. This chip is housed in a 56-pin QFN package.
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