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A low phase noise LC-VCO with a high-Q inductor fabricated by wafer level package technology 采用晶圆级封装技术制造的低相位噪声高q电感LC-VCO
2008 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2008-07-15 DOI: 10.1109/RFIC.2008.4561400
K. Ohashi, Y. Kobayashi, H. Ito, K. Okada, H. Hatakeyama, T. Aizawa, T. Ito, R. Yamauchi, K. Masu
{"title":"A low phase noise LC-VCO with a high-Q inductor fabricated by wafer level package technology","authors":"K. Ohashi, Y. Kobayashi, H. Ito, K. Okada, H. Hatakeyama, T. Aizawa, T. Ito, R. Yamauchi, K. Masu","doi":"10.1109/RFIC.2008.4561400","DOIUrl":"https://doi.org/10.1109/RFIC.2008.4561400","url":null,"abstract":"This paper presents a CMOS voltage controlled oscillator (VCO) with a high-Q inductor fabricated by using a commercial wafer-level-package (WLP) technology. A new topology suitable for CMOS VCOs with high-Q WLP inductors is proposed. Measured Q of a WLP inductor is 40 in differential mode at around 1.9 GHz. A phase noise is -134.4 dBc/Hz at a 1 MHz offset for 1.9 GHz carrier frequency, and a FoM is -193 dBc/Hz. The VCO with the WLP inductor improves a phase noise of 6.4 dB as compared to VCOs with conventional on-chip inductors.","PeriodicalId":253375,"journal":{"name":"2008 IEEE Radio Frequency Integrated Circuits Symposium","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125356326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Study of the different coupling mechanisms between a 4 GHz PPA and a 5–7 GHz LC-VCO 4 GHz PPA与5-7 GHz LC-VCO不同耦合机制的研究
2008 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2008-07-15 DOI: 10.1109/RFIC.2008.4561480
S. Bronckers, G. Vandersteen, L. De Locht, G. van der Plas, Y. Rolain
{"title":"Study of the different coupling mechanisms between a 4 GHz PPA and a 5–7 GHz LC-VCO","authors":"S. Bronckers, G. Vandersteen, L. De Locht, G. van der Plas, Y. Rolain","doi":"10.1109/RFIC.2008.4561480","DOIUrl":"https://doi.org/10.1109/RFIC.2008.4561480","url":null,"abstract":"The coupling of the transmitted RF signal of the power amplifier (PA) into the sensitive voltage controlled oscillator (VCO) of a transceiver can cause failure of the RFIC. It is not obvious for the designer to identify which coupling mechanism can be held responsible for the degradation of the VCO. Thus it remains an open problem to decide which appropriate countermeasure should be taken. Different experiments are carried out on a 0.13 mum CMOS 4 GHz PPA and a 5-7 GHz LC-VCO to gain insight in the different coupling mechanisms.","PeriodicalId":253375,"journal":{"name":"2008 IEEE Radio Frequency Integrated Circuits Symposium","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126742857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A 0.13 μm CMOS 90 dB variable gain pre-power amplifier using robust linear-in-dB attenuator 一种0.13 μm CMOS 90 dB可变增益前置功率放大器，采用鲁棒的dB内线性衰减器
2008 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2008-07-15 DOI: 10.1109/RFIC.2008.4561527
Y. Araki, T. Hashimoto, S. Otaka
{"title":"A 0.13 μm CMOS 90 dB variable gain pre-power amplifier using robust linear-in-dB attenuator","authors":"Y. Araki, T. Hashimoto, S. Otaka","doi":"10.1109/RFIC.2008.4561527","DOIUrl":"https://doi.org/10.1109/RFIC.2008.4561527","url":null,"abstract":"A 0.13um CMOS pre-power amplifier with 90dB gain range is fabricated. The pre-power amplifier consists of 4 variable attenuators and 3 fixed gain amplifiers, where the proposed attenuator suppresses the attenuation variation due to Vth variation. The pre-power amplifier outputs +4dBm with 75mW and -80dBm with 65mW. The ACPR is -48dBc and the EVM is less than 1.0% at Pout = +4dBm. The attenuation variation of less than +/-5dB is achieved.","PeriodicalId":253375,"journal":{"name":"2008 IEEE Radio Frequency Integrated Circuits Symposium","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122698571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 77GHz 4-channel automotive radar transceiver in SiGe 一个77GHz 4通道汽车雷达收发器
2008 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2008-07-15 DOI: 10.1109/RFIC.2008.4561425
H. Forstner, H. Knapp, H. Jager, E. Kolmhofer, J. Platz, F. Starzer, M. Treml, A. Schinko, G. Birschkus, J. Bock, K. Aufinger, R. Lachner, T. Meister, H. Schäfer, D. Lukashevich, S. Boguth, A. Fischer, F. Reininger, L. Maurer, J. Minichshofer, D. Steinbuch
{"title":"A 77GHz 4-channel automotive radar transceiver in SiGe","authors":"H. Forstner, H. Knapp, H. Jager, E. Kolmhofer, J. Platz, F. Starzer, M. Treml, A. Schinko, G. Birschkus, J. Bock, K. Aufinger, R. Lachner, T. Meister, H. Schäfer, D. Lukashevich, S. Boguth, A. Fischer, F. Reininger, L. Maurer, J. Minichshofer, D. Steinbuch","doi":"10.1109/RFIC.2008.4561425","DOIUrl":"https://doi.org/10.1109/RFIC.2008.4561425","url":null,"abstract":"A fully integrated 4-channel automotive radar transceiver chip, integrated in a 200-GHz SiGe:C production technology, is presented. With a typical transmit power of 2 x +7 dBm at the antenna ports and all functions active, the chip draws a current of about 600 mA from a single 5.5 V supply. The design permits FMCW operation in the 76 to 77 GHz band at chip-backside temperatures from -40degC to +125degC.","PeriodicalId":253375,"journal":{"name":"2008 IEEE Radio Frequency Integrated Circuits Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129594828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 141
An ultra low power 130nm CMOS direct conversion transceiver for IEEE802.15.4 IEEE802.15.4超低功耗130nm CMOS直接转换收发器
2008 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2008-07-15 DOI: 10.1109/RFIC.2008.4561434
C. Bernier, F. Hameau, G. Billiot, E. Foucauld, S. Robinet, J. Durupt, F. Dehmas, E. Mercier, P. Vincent, L. Ouvry, D. Lattard, M. Gary, C. Bour, J. Prouvée, S. Dumas
{"title":"An ultra low power 130nm CMOS direct conversion transceiver for IEEE802.15.4","authors":"C. Bernier, F. Hameau, G. Billiot, E. Foucauld, S. Robinet, J. Durupt, F. Dehmas, E. Mercier, P. Vincent, L. Ouvry, D. Lattard, M. Gary, C. Bour, J. Prouvée, S. Dumas","doi":"10.1109/RFIC.2008.4561434","DOIUrl":"https://doi.org/10.1109/RFIC.2008.4561434","url":null,"abstract":"A fully integrated 2.4 GHz transceiver based on the IEEE802.15.4 specification has been designed using a 130 nm CMOS technology. Concurrent system and design optimizations were required to reach an energy efficiency of 21.5 nJ/bit in RX mode and 32.5 nJ/bit in TX modes, respectively, at a data rate of 250 kbit/s. The circuit includes a -5 dBm transmitter, a -81 dBm sensitivity receiver, an integer N PLL with 5 MHz reference, a dual I/Q 3-bit ADC at 4 MS/s, an analog RSSI with 8-bit ADC at 8 kS/s and an integrated SPDT TX/RX switch to a 100 Omega differential antenna port. The chip consumes 5.4 mW in RX mode and 8.1 mW in TX mode under 1.2 V.","PeriodicalId":253375,"journal":{"name":"2008 IEEE Radio Frequency Integrated Circuits Symposium","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129093071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
An 11.5% frequency tuning, −184 dBc/Hz noise FOM 54 GHz VCO 来自54ghz压控振荡器的11.5%频率调谐，−184 dBc/Hz噪声
2008 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2008-07-15 DOI: 10.1109/RFIC.2008.4561523
S. Bozzola, D. Guermandi, A. Mazzanti, F. Svelto
{"title":"An 11.5% frequency tuning, −184 dBc/Hz noise FOM 54 GHz VCO","authors":"S. Bozzola, D. Guermandi, A. Mazzanti, F. Svelto","doi":"10.1109/RFIC.2008.4561523","DOIUrl":"https://doi.org/10.1109/RFIC.2008.4561523","url":null,"abstract":"This work presents a robust, low area, spectral pure 65 nm VCO for mm-wave applications. The varactor, an inversion mode MOS, takes advantage of the minimum feature provided by the technology to optimize capacitance tuning range and Q. The inductor is a 1 turn spiral. A combination of digital and analog tuning is chosen to lower VCO gain. Prototypes show the following measured results: 11.5% frequency tuning range around 54 GHz, phase noise at 10 MHz of -116 dBc/Hz and -122 dBc/Hz maximum and minimum in band, respectively. Power consumption is 7.2 mW.","PeriodicalId":253375,"journal":{"name":"2008 IEEE Radio Frequency Integrated Circuits Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128122593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
A 1.0 V, 2.5 mW, transformer noise-canceling UWB CMOS LNA 一个1.0 V, 2.5 mW，变压器降噪UWB CMOS LNA
2008 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2008-07-15 DOI: 10.1109/RFIC.2008.4561484
T. Kihara, T. Matsuoka, K. Taniguchi
{"title":"A 1.0 V, 2.5 mW, transformer noise-canceling UWB CMOS LNA","authors":"T. Kihara, T. Matsuoka, K. Taniguchi","doi":"10.1109/RFIC.2008.4561484","DOIUrl":"https://doi.org/10.1109/RFIC.2008.4561484","url":null,"abstract":"We present a transformer noise-canceling ultra-wideband (UWB) CMOS LNA based on a common-gate topology. A transformer, composed of an input inductor and shunt peaking inductor, partly cancels the noise originating from a common-gate transistor. The combination of the transformer with an output series inductor provides wideband input impedance matching. The LNA, implemented with 90-nm digital CMOS technology occupies 0.10 mm2 and achieves S11 Lt -10 dB, NF Lt 3.3 dB, and S21 Gt 7.8 dB across 3.1-10.6 GHz with a power consumption of 2.5 mW from a 1.0-V supply. These results show that the proposed topology is the most suitable for low-power and low-voltage UWB CMOS LNAs.","PeriodicalId":253375,"journal":{"name":"2008 IEEE Radio Frequency Integrated Circuits Symposium","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121850001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A 2.2dB NF, 4.9–6GHz direct conversion multi-standard RF receiver front-end in 90nm CMOS 2.2dB NF, 4.9-6GHz直接转换多标准射频接收机前端，采用90nm CMOS
2008 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2008-07-15 DOI: 10.1109/RFIC.2008.4561513
Brent R. Carlton, J. Duster, Stewart S. Taylor, J.-H.C. Zhan
{"title":"A 2.2dB NF, 4.9–6GHz direct conversion multi-standard RF receiver front-end in 90nm CMOS","authors":"Brent R. Carlton, J. Duster, Stewart S. Taylor, J.-H.C. Zhan","doi":"10.1109/RFIC.2008.4561513","DOIUrl":"https://doi.org/10.1109/RFIC.2008.4561513","url":null,"abstract":"A multi-standard direct conversion receiver achieves 2.2 dB NF at 6 GHz with a 15 kHz flicker noise corner. 1 dB RF bandwidth is 4.9-6 GHz, power dissipation is 56 mW from 1.3 V and active die area is less than 1.2 mm2, including the input matching network. Inband P1 dB and IIP3 at maximum gain (39 dB) are -30 dBm and -18 dBm, respectively, and three gain steps of 6 dB are provided. DC offset from self mixing is less than 10 mV.","PeriodicalId":253375,"journal":{"name":"2008 IEEE Radio Frequency Integrated Circuits Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132225329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A digital ΔΣ RF signal generator for mobile communication transmitters in 90nm CMOS 用于90纳米CMOS移动通信发射机的数字ΔΣ射频信号发生器
2008 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2008-07-15 DOI: 10.1109/RFIC.2008.4561375
A. Frappé, B. Stefanelli, A. Flament, Andreas Kaiser, A. Cathelin
{"title":"A digital ΔΣ RF signal generator for mobile communication transmitters in 90nm CMOS","authors":"A. Frappé, B. Stefanelli, A. Flament, Andreas Kaiser, A. Cathelin","doi":"10.1109/RFIC.2008.4561375","DOIUrl":"https://doi.org/10.1109/RFIC.2008.4561375","url":null,"abstract":"The presented digital RF signal generator in 90 nm CMOS uses 1-bit DeltaSigma modulation and targets mobile communication terminals. A 50 MHz bandwidth centered on 1 GHz can be achieved when the circuit is clocked at 4 GHz. Signals up to 3 GHz can be synthesized when using the first image band. The peak output power into a 100 Omega diff. load is 3.1 dBm with 53.6 dB SNDR. The digital core employs redundant arithmetic, precomputed non-exact quantization and differential dynamic logic. The digital core consumes 49 mW at maximum clock frequency. Active area is 0.15 mm2.","PeriodicalId":253375,"journal":{"name":"2008 IEEE Radio Frequency Integrated Circuits Symposium","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133240811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A 3x3mm2 embedded-wafer-level packaged WCDMA GaAs HBT power amplifier module with integrated Si DC power management IC 一种3x3mm2的嵌入式晶圆级封装WCDMA GaAs HBT功率放大器模块，集成了Si直流电源管理IC
2008 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2008-07-15 DOI: 10.1109/RFIC.2008.4561465
G. Hau, Shih Hsu, Y. Aoki, T. Wakabayashi, N. Furuhata, Y. Mikado
{"title":"A 3x3mm2 embedded-wafer-level packaged WCDMA GaAs HBT power amplifier module with integrated Si DC power management IC","authors":"G. Hau, Shih Hsu, Y. Aoki, T. Wakabayashi, N. Furuhata, Y. Mikado","doi":"10.1109/RFIC.2008.4561465","DOIUrl":"https://doi.org/10.1109/RFIC.2008.4561465","url":null,"abstract":"This paper presents a highly compact 3 times 3 mm2 WCDMA power amplifier (PA) module which integrates a GaAs HBT MMIC PA and a Si DC power management IC into one single package. A closed-loop controlled DC-DC buck converter allows the power management IC to adaptively optimize the PA collector voltage as a function of output power and thereby reduce current consumption under backoff operation. A novel embedded-wafer-level-package (EWLP) technology is developed for module miniaturization. Redistribution layers and bumps are formed on the Si IC to create the wafer level package (WLP). The EWLP is then fabricated by embedding the WLP IC inside the core of the module. The MMIC PA is mounted on the surface of the module, creating a vertical integration for size reduction. The PA module (PAM) achieves excellent current reduction over a wide range of output power (Pout) up to 27.5 dBm, while maintaining ACLR1 below -40 dBc. At 16 dBm and 24 dBm Pout, the current consumptions are reduced from 162 mA and 370 mA, to 65 mA and 237 mA, respectively, compared to the conventional PA.","PeriodicalId":253375,"journal":{"name":"2008 IEEE Radio Frequency Integrated Circuits Symposium","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128907573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
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