C. Bernier, F. Hameau, G. Billiot, E. Foucauld, S. Robinet, J. Durupt, F. Dehmas, E. Mercier, P. Vincent, L. Ouvry, D. Lattard, M. Gary, C. Bour, J. Prouvée, S. Dumas
{"title":"IEEE802.15.4超低功耗130nm CMOS直接转换收发器","authors":"C. Bernier, F. Hameau, G. Billiot, E. Foucauld, S. Robinet, J. Durupt, F. Dehmas, E. Mercier, P. Vincent, L. Ouvry, D. Lattard, M. Gary, C. Bour, J. Prouvée, S. Dumas","doi":"10.1109/RFIC.2008.4561434","DOIUrl":null,"url":null,"abstract":"A fully integrated 2.4 GHz transceiver based on the IEEE802.15.4 specification has been designed using a 130 nm CMOS technology. Concurrent system and design optimizations were required to reach an energy efficiency of 21.5 nJ/bit in RX mode and 32.5 nJ/bit in TX modes, respectively, at a data rate of 250 kbit/s. The circuit includes a -5 dBm transmitter, a -81 dBm sensitivity receiver, an integer N PLL with 5 MHz reference, a dual I/Q 3-bit ADC at 4 MS/s, an analog RSSI with 8-bit ADC at 8 kS/s and an integrated SPDT TX/RX switch to a 100 Omega differential antenna port. The chip consumes 5.4 mW in RX mode and 8.1 mW in TX mode under 1.2 V.","PeriodicalId":253375,"journal":{"name":"2008 IEEE Radio Frequency Integrated Circuits Symposium","volume":"82 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"An ultra low power 130nm CMOS direct conversion transceiver for IEEE802.15.4\",\"authors\":\"C. Bernier, F. Hameau, G. Billiot, E. Foucauld, S. Robinet, J. Durupt, F. Dehmas, E. Mercier, P. Vincent, L. Ouvry, D. Lattard, M. Gary, C. Bour, J. Prouvée, S. Dumas\",\"doi\":\"10.1109/RFIC.2008.4561434\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A fully integrated 2.4 GHz transceiver based on the IEEE802.15.4 specification has been designed using a 130 nm CMOS technology. Concurrent system and design optimizations were required to reach an energy efficiency of 21.5 nJ/bit in RX mode and 32.5 nJ/bit in TX modes, respectively, at a data rate of 250 kbit/s. The circuit includes a -5 dBm transmitter, a -81 dBm sensitivity receiver, an integer N PLL with 5 MHz reference, a dual I/Q 3-bit ADC at 4 MS/s, an analog RSSI with 8-bit ADC at 8 kS/s and an integrated SPDT TX/RX switch to a 100 Omega differential antenna port. The chip consumes 5.4 mW in RX mode and 8.1 mW in TX mode under 1.2 V.\",\"PeriodicalId\":253375,\"journal\":{\"name\":\"2008 IEEE Radio Frequency Integrated Circuits Symposium\",\"volume\":\"82 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-07-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 IEEE Radio Frequency Integrated Circuits Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RFIC.2008.4561434\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE Radio Frequency Integrated Circuits Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC.2008.4561434","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An ultra low power 130nm CMOS direct conversion transceiver for IEEE802.15.4
A fully integrated 2.4 GHz transceiver based on the IEEE802.15.4 specification has been designed using a 130 nm CMOS technology. Concurrent system and design optimizations were required to reach an energy efficiency of 21.5 nJ/bit in RX mode and 32.5 nJ/bit in TX modes, respectively, at a data rate of 250 kbit/s. The circuit includes a -5 dBm transmitter, a -81 dBm sensitivity receiver, an integer N PLL with 5 MHz reference, a dual I/Q 3-bit ADC at 4 MS/s, an analog RSSI with 8-bit ADC at 8 kS/s and an integrated SPDT TX/RX switch to a 100 Omega differential antenna port. The chip consumes 5.4 mW in RX mode and 8.1 mW in TX mode under 1.2 V.
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