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2008 IEEE Radio Frequency Integrated Circuits Symposium最新文献

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Process dependence of 0.11 μm RF CMOS on high-resistivity substrate for System on Chip (SOC) application 片上系统(SOC) 0.11 μm RF CMOS在高电阻率衬底上的工艺依赖性
2008 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2008-07-15 DOI: 10.1109/RFIC.2008.4561499
T. Ohguro, K. Kojima, N. Momo, H. Momose, Y. Toyoshima
{"title":"Process dependence of 0.11 μm RF CMOS on high-resistivity substrate for System on Chip (SOC) application","authors":"T. Ohguro, K. Kojima, N. Momo, H. Momose, Y. Toyoshima","doi":"10.1109/RFIC.2008.4561499","DOIUrl":"https://doi.org/10.1109/RFIC.2008.4561499","url":null,"abstract":"High-resistivity substrate with beyond 1000 ohm-cm realizes high performance in terms of inductor, antenna, MIM capacitor and substrate noise for high- frequency applications. However, this wafer has serious problems for mixed-signal, RF and digital circuits. Those are reduction of high resistivity during sinter process such as 400degC, larger leakage current between nwells, extreme lower snap-back voltage in latch-up behavior and higher RF noise. The RF noise is proportional to square root of Si substrate resistivity in our experience. In this paper, it is shown that these problems can be resolved by the optimum wafer fabrication process and the additional ion implantation.","PeriodicalId":253375,"journal":{"name":"2008 IEEE Radio Frequency Integrated Circuits Symposium","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130876589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A temperature-compensated low-noise digitally-controlled crystal oscillator for multi-standard applications 一种温度补偿低噪声数字控制晶体振荡器，适用于多标准应用
2008 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2008-07-15 DOI: 10.1109/RFIC.2008.4561493
Ming-Da Tsai, C.W. Yeh, Yi-Hsien Cho, L. Ke, P. Chen, G. Dehng
{"title":"A temperature-compensated low-noise digitally-controlled crystal oscillator for multi-standard applications","authors":"Ming-Da Tsai, C.W. Yeh, Yi-Hsien Cho, L. Ke, P. Chen, G. Dehng","doi":"10.1109/RFIC.2008.4561493","DOIUrl":"https://doi.org/10.1109/RFIC.2008.4561493","url":null,"abstract":"This paper presents an integrated 26-MHz digitally-controlled crystal oscillator (DCXO) with temperature compensation function for multi-standard cellular applications, that achieves a phase noise of -154 and -159 dBc/Hz at 10 kHz and 100 kHz offset, respectively. The frequency instability over temperature is compensated by built-in temperature sensor and compensating capacitor. The frequency instability from -10 to 55 degC is about +/- 1 ppm. The AFC frequency tuning is done by a digitally-controlled metal-oxide-metal capacitor array that is 13-bit thermometer decoded. The DCXO is implemented in a 0.13-mum CMOS technology.","PeriodicalId":253375,"journal":{"name":"2008 IEEE Radio Frequency Integrated Circuits Symposium","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121827583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
A 2.5-dB NF 3.1–10.6-GHz CMOS UWB LNA with small group-delay-variation 具有小群延迟变化的2.5 db NF 3.1 - 10.6 ghz CMOS UWB LNA
2008 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2008-07-15 DOI: 10.1109/RFIC.2008.4561486
Jen-How Lee, Chi-Chen Chen, Hong-Yu Yang, Yo‐Sheng Lin
{"title":"A 2.5-dB NF 3.1–10.6-GHz CMOS UWB LNA with small group-delay-variation","authors":"Jen-How Lee, Chi-Chen Chen, Hong-Yu Yang, Yo‐Sheng Lin","doi":"10.1109/RFIC.2008.4561486","DOIUrl":"https://doi.org/10.1109/RFIC.2008.4561486","url":null,"abstract":"A 3.1-10.6-GHz ultra-wideband low-noise amplifier (UWB LNA) with excellent phase linearity property (group-delay-variation is only plusmn16.7 ps across the whole band) using standard 0.13 mum CMOS technology is reported. To achieve high and flat gain and small group-delay-variation at the same time, the inductive peaking technique is adopted in the output stage for bandwidth enhancement. The UWB LNA dissipates 10.68 mW power and achieves input return loss (S11) of -17.5 ~ -33.6 dB, output return loss (S22) of -14.4 ~ -16.3 dB, flat forward gain (S21) of 7.92 plusmn 0.23 dB, and reverse isolation (S12) of -25.8 ~ -41.9 dB over the 3.1-10.6 GHz band of interest. State-of-the-art noise figure (NF) of 2.5 dB is achieved at 10.5 GHz. The measured 1-dB compression point (P1dB) and input third-order inter-modulation point (IIP3) were -14 dBm and -4 dBm, respectively, at 6 GHz.","PeriodicalId":253375,"journal":{"name":"2008 IEEE Radio Frequency Integrated Circuits Symposium","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122444097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
VCO design for 60 GHz applications using differential shielded inductors in 0.13 μm CMOS 采用0.13 μm CMOS差分屏蔽电感的60 GHz应用压控振荡器设计
2008 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2008-07-15 DOI: 10.1109/RFIC.2008.4561403
J. Borremans, M. Dehan, K. Scheir, Maarten Kuijk, P. Wambacq
{"title":"VCO design for 60 GHz applications using differential shielded inductors in 0.13 μm CMOS","authors":"J. Borremans, M. Dehan, K. Scheir, Maarten Kuijk, P. Wambacq","doi":"10.1109/RFIC.2008.4561403","DOIUrl":"https://doi.org/10.1109/RFIC.2008.4561403","url":null,"abstract":"With the increasing interest in 60 GHz applications, low-cost CMOS circuit solutions emerge. The poor performance of CMOS devices at millimeter-wave frequencies complicates the design. In this work, we present two low-area VCOs covering the license-free 60 GHz band, using differential shielded (slow-wave) transmission line inductors. We discuss design and provide compact modeling of these inductors, compatible with stringent metal density rules of scaled CMOS. Measured phase noise below -90 dBc/Hz at 1 MHz offset is achieved, at a consumption of 3.9 mW at 1 V. The tuning range exceeds 10 %, for a tuning voltage restricted from ground to the supply.","PeriodicalId":253375,"journal":{"name":"2008 IEEE Radio Frequency Integrated Circuits Symposium","volume":"34 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131870236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 54
A 5-GHz, 30-dBm, 0.9-dB insertion loss single-pole double-throw T/R switch in 90nm CMOS 5 ghz、30 dbm、0.9 db插入损耗单极双掷T/R开关
2008 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2008-07-15 DOI: 10.1109/RFIC.2008.4561444
C. Fu, S. S. Taylor, C. Kuo
{"title":"A 5-GHz, 30-dBm, 0.9-dB insertion loss single-pole double-throw T/R switch in 90nm CMOS","authors":"C. Fu, S. S. Taylor, C. Kuo","doi":"10.1109/RFIC.2008.4561444","DOIUrl":"https://doi.org/10.1109/RFIC.2008.4561444","url":null,"abstract":"A 5 GHz, 30-dBm CMOS T/R switch implemented in 90 nm CMOS is reported. A body isolation technique is employed and optimized for power handling capability. Inductors are employed with the transistor switches for parallel resonance to improve isolation. Thick oxide NMOS transistors are used for the switching transistors and placed inside the inductors to reduce the active chip area to approximately 0.2 mm2. 0.9-dB insertion loss for both TX and RX modes is achieved with a 5-V control voltage.","PeriodicalId":253375,"journal":{"name":"2008 IEEE Radio Frequency Integrated Circuits Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131930551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 25 GHz 3.3 dB NF low noise amplifier based upon slow wave transmission lines and the 0.18 μm CMOS technology 基于慢波传输线和0.18 μm CMOS技术的25 GHz 3.3 dB NF低噪声放大器
2008 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2008-07-15 DOI: 10.1109/RFIC.2008.4561457
A. Sayag, S. Levin, D. Regev, D. Zfira, S. Shapira, D. Goren, D. Ritter
{"title":"A 25 GHz 3.3 dB NF low noise amplifier based upon slow wave transmission lines and the 0.18 μm CMOS technology","authors":"A. Sayag, S. Levin, D. Regev, D. Zfira, S. Shapira, D. Goren, D. Ritter","doi":"10.1109/RFIC.2008.4561457","DOIUrl":"https://doi.org/10.1109/RFIC.2008.4561457","url":null,"abstract":"A 25 GHz low noise amplifier using standard 0.18 mum digital CMOS technology is presented. Matching networks were based upon slow wave transmissions lines. Peak gain of 12.8 dB at 24 GHz and in-band minimum noise figure less than 4 dB were obtained at a power consumption of 8 mW. These record results demonstrate the usefulness of the slow wave transmission line approach. A compact model of slow wave transmission lines is briefly described as well.","PeriodicalId":253375,"journal":{"name":"2008 IEEE Radio Frequency Integrated Circuits Symposium","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133373816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
A 65nm CMOS 30dBm class-E RF power amplifier with 60% power added efficiency 65nm CMOS 30dBm e类射频功率放大器，功率增加效率60%
2008 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2008-07-15 DOI: 10.1109/RFIC.2008.4561404
M. Apostolidou, M. Heijden, D. Leenaerts, J. Sonsky, A. Heringa, I. Volokhine
{"title":"A 65nm CMOS 30dBm class-E RF power amplifier with 60% power added efficiency","authors":"M. Apostolidou, M. Heijden, D. Leenaerts, J. Sonsky, A. Heringa, I. Volokhine","doi":"10.1109/RFIC.2008.4561404","DOIUrl":"https://doi.org/10.1109/RFIC.2008.4561404","url":null,"abstract":"A 30 dBm single-ended class-E RF power amplifier (PA) is fabricated in 65 nm CMOS technology. The PA is a cascode stage formed by a standard thin-oxide device and a high voltage extended-drain thick-oxide device. Both devices are implemented in a standard sub-micron CMOS technology without using extra masks or processing steps. The proposed PA uses an innovative self-biasing technique to ensure high power-added efficiency (PAE) at both high output power (Pout) and power back-off levels. At 2 GHz, the PA achieves a PAE of 60% at a Pout of 30 dBm and a PAE of 40% at 16 dB back-off.","PeriodicalId":253375,"journal":{"name":"2008 IEEE Radio Frequency Integrated Circuits Symposium","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133896661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
Nonlinear behavioral modeling of oscillators in VHDL-AMS using Artificial Neural Networks 基于人工神经网络的VHDL-AMS振荡器非线性行为建模
2008 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2008-07-15 DOI: 10.1109/RFIC.2008.4561531
M. Kraemer, D. Dragomirescu, R. Plana
{"title":"Nonlinear behavioral modeling of oscillators in VHDL-AMS using Artificial Neural Networks","authors":"M. Kraemer, D. Dragomirescu, R. Plana","doi":"10.1109/RFIC.2008.4561531","DOIUrl":"https://doi.org/10.1109/RFIC.2008.4561531","url":null,"abstract":"In this paper an approach to behavioral modeling of microwave oscillators is described. The presented model takes into account start-up, steady state behavior and phase noise. To describe the nonlinearities, an artificial neural network (ANN) is employed. The dynamic behavior of the oscillator is described by a system of differential equations that are solved in VHDL-AMS. As opposed to input-output models of microwave devices, this paper presents a self sustaining oscillation, which starts from a small injected excitation (e.g. noise) and ends in a stable limit cycle. Additionally, the phase noise characteristics of the oscillator in the 1/f2 and flat region are emulated.","PeriodicalId":253375,"journal":{"name":"2008 IEEE Radio Frequency Integrated Circuits Symposium","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125574863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Improved RF-performance of sub-micron CMOS transistors by asymmetrically fingered device layout 采用非对称指形器件布局提高了亚微米CMOS晶体管的射频性能
2008 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2008-07-15 DOI: 10.1109/RFIC.2008.4561500
C. Weyers, D. Kehrer, J. Kunze, P. Mayr, D. Siprak, M. Tiebout, J. Hausner, U. Langmann
{"title":"Improved RF-performance of sub-micron CMOS transistors by asymmetrically fingered device layout","authors":"C. Weyers, D. Kehrer, J. Kunze, P. Mayr, D. Siprak, M. Tiebout, J. Hausner, U. Langmann","doi":"10.1109/RFIC.2008.4561500","DOIUrl":"https://doi.org/10.1109/RFIC.2008.4561500","url":null,"abstract":"This paper presents novel MOS-transistor layouts for analog RF applications. Asymmetrical drain and source diffusion areas as well as their contacting metal stacks are adjusted to improve the transistor performance. These modifications allow for increased device currents and reduced parasitic wiring capacitances simultaneously. Ring oscillators with transistors of identical channel width and length fabricated in a 65 nm digital CMOS technology are used for verification. An increase of 14% in oscillation frequency compared to classical multi-finger layouts corroborates the improvement by these modifications.","PeriodicalId":253375,"journal":{"name":"2008 IEEE Radio Frequency Integrated Circuits Symposium","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126498666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 600MHz CMOS OFDM LINC transmitter with a 7 bit digital phase modulator 带有7位数字相位调制器的600MHz CMOS OFDM LINC发射机
2008 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2008-07-15 DOI: 10.1109/RFIC.2008.4561528
Kwan-Woo Kim, S. Byun, K. Lim, Chang-Ho Lee, J. Laskar
{"title":"A 600MHz CMOS OFDM LINC transmitter with a 7 bit digital phase modulator","authors":"Kwan-Woo Kim, S. Byun, K. Lim, Chang-Ho Lee, J. Laskar","doi":"10.1109/RFIC.2008.4561528","DOIUrl":"https://doi.org/10.1109/RFIC.2008.4561528","url":null,"abstract":"This paper presents a new architecture for a LINC transmitter adopting a digital phase modulator (DPM). The DPM uses a 7 bit digital input to directly modulate the RF phase of each path, thus simplifying gain/phase mismatch compensation. Furthermore, this feature needs only one set of test signals for gain and phase mismatch detection. The implemented LINC transmitter IC consumes 140 mA from a 1.9V supply including an LC quadrature VCO, two DPMs, and two PA driver amplifiers, and it transmits a 6 MHz bandwidth 64-QAM OFDM signal in the UHF TV band with external switching PAs and a power combiner.","PeriodicalId":253375,"journal":{"name":"2008 IEEE Radio Frequency Integrated Circuits Symposium","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129470175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
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