Improved RF-performance of sub-micron CMOS transistors by asymmetrically fingered device layout

Abstract

This paper presents novel MOS-transistor layouts for analog RF applications. Asymmetrical drain and source diffusion areas as well as their contacting metal stacks are adjusted to improve the transistor performance. These modifications allow for increased device currents and reduced parasitic wiring capacitances simultaneously. Ring oscillators with transistors of identical channel width and length fabricated in a 65 nm digital CMOS technology are used for verification. An increase of 14% in oscillation frequency compared to classical multi-finger layouts corroborates the improvement by these modifications.