65nm CMOS 30dBm e类射频功率放大器，功率增加效率60%

2008 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2008-07-15 DOI:10.1109/RFIC.2008.4561404

M. Apostolidou, M. Heijden, D. Leenaerts, J. Sonsky, A. Heringa, I. Volokhine

{"title":"65nm CMOS 30dBm e类射频功率放大器，功率增加效率60%","authors":"M. Apostolidou, M. Heijden, D. Leenaerts, J. Sonsky, A. Heringa, I. Volokhine","doi":"10.1109/RFIC.2008.4561404","DOIUrl":null,"url":null,"abstract":"A 30 dBm single-ended class-E RF power amplifier (PA) is fabricated in 65 nm CMOS technology. The PA is a cascode stage formed by a standard thin-oxide device and a high voltage extended-drain thick-oxide device. Both devices are implemented in a standard sub-micron CMOS technology without using extra masks or processing steps. The proposed PA uses an innovative self-biasing technique to ensure high power-added efficiency (PAE) at both high output power (Pout) and power back-off levels. At 2 GHz, the PA achieves a PAE of 60% at a Pout of 30 dBm and a PAE of 40% at 16 dB back-off.","PeriodicalId":253375,"journal":{"name":"2008 IEEE Radio Frequency Integrated Circuits Symposium","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"34","resultStr":"{\"title\":\"A 65nm CMOS 30dBm class-E RF power amplifier with 60% power added efficiency\",\"authors\":\"M. Apostolidou, M. Heijden, D. Leenaerts, J. Sonsky, A. Heringa, I. Volokhine\",\"doi\":\"10.1109/RFIC.2008.4561404\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 30 dBm single-ended class-E RF power amplifier (PA) is fabricated in 65 nm CMOS technology. The PA is a cascode stage formed by a standard thin-oxide device and a high voltage extended-drain thick-oxide device. Both devices are implemented in a standard sub-micron CMOS technology without using extra masks or processing steps. The proposed PA uses an innovative self-biasing technique to ensure high power-added efficiency (PAE) at both high output power (Pout) and power back-off levels. At 2 GHz, the PA achieves a PAE of 60% at a Pout of 30 dBm and a PAE of 40% at 16 dB back-off.\",\"PeriodicalId\":253375,\"journal\":{\"name\":\"2008 IEEE Radio Frequency Integrated Circuits Symposium\",\"volume\":\"28 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-07-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"34\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 IEEE Radio Frequency Integrated Circuits Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RFIC.2008.4561404\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE Radio Frequency Integrated Circuits Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC.2008.4561404","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 34

摘要

采用65nm CMOS工艺制备了30dbm单端e类射频功率放大器(PA)。PA是由一个标准的薄氧化装置和一个高压延伸漏厚氧化装置组成的级联级。这两种器件都采用标准的亚微米CMOS技术，无需使用额外的掩模或处理步骤。所提出的PA采用了一种创新的自偏置技术，以确保在高输出功率(Pout)和功率回退水平下的高功率附加效率(PAE)。在2ghz时，PA在30dbm输出时的PAE为60%，在16db后退时的PAE为40%。

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A 65nm CMOS 30dBm class-E RF power amplifier with 60% power added efficiency

A 30 dBm single-ended class-E RF power amplifier (PA) is fabricated in 65 nm CMOS technology. The PA is a cascode stage formed by a standard thin-oxide device and a high voltage extended-drain thick-oxide device. Both devices are implemented in a standard sub-micron CMOS technology without using extra masks or processing steps. The proposed PA uses an innovative self-biasing technique to ensure high power-added efficiency (PAE) at both high output power (Pout) and power back-off levels. At 2 GHz, the PA achieves a PAE of 60% at a Pout of 30 dBm and a PAE of 40% at 16 dB back-off.

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2008 IEEE Radio Frequency Integrated Circuits Symposium

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