A GSM/EDGE transmitter in 0.13-μm CMOS using offset phase locked loop and direct conversion architecture

Abstract

A GSM/EDGE transmitter implemented in 0.13-mum CMOS using offset phase locked loop and direct conversion architecture is presented. The transmitter consists of a DCT, an OPLL with a TXVCO, a fractional-N synthesizer with a RFVCO and LDO regulators. The transmitter delivers 1.5 dBm output power with 1.2deg rms phase error and the modulation spectrum at 400 kHz offset is better than -62 dBc in high band GSM mode. In high band EDGE mode, it has maximum 4 dBm output power with 0.5 dB gain step per bit for 36 dB dynamic range and 2% rms error vector magnitude. The current consumption of high band is 171 mA at GSM mode and 169 mA at EDGE mode under proper output power level for PA. This chip is housed in a 56-pin QFN package.