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Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)最新文献

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Signal coding technique and CMOS gates for strongly fault-secure combinational functional blocks 强故障安全组合功能块的信号编码技术和CMOS门
Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223) Pub Date : 1998-11-02 DOI: 10.1109/DFTVS.1998.732164
C. Metra, M. Favalli, B. Riccò
{"title":"Signal coding technique and CMOS gates for strongly fault-secure combinational functional blocks","authors":"C. Metra, M. Favalli, B. Riccò","doi":"10.1109/DFTVS.1998.732164","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732164","url":null,"abstract":"This paper proposes a signal coding technique (using frequency redundancy) and CMOS gates to allow the design of functional blocks of self-checking circuits whose correct operation is guaranteed with respect to a wide set of possible, internal faults. These include not only conventional stuck-ats, but also transistor stuck-ons, transistor stuck-opens and resistive bridgings. Compared to the alternative, existing solution, the technique proposed here does not imply any critical constraint on the circuit electrical parameters. Hence it is better suited to the design of next generation, deep submicron technology circuits.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116665978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A systematic approach for diagnosing multiple delay faults 多时延故障的系统诊断方法
Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223) Pub Date : 1998-11-02 DOI: 10.1109/DFTVS.1998.732168
Jayabrata Ghosh-Dastidar, N. Touba
{"title":"A systematic approach for diagnosing multiple delay faults","authors":"Jayabrata Ghosh-Dastidar, N. Touba","doi":"10.1109/DFTVS.1998.732168","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732168","url":null,"abstract":"In the presence of multiple delay faults, automated diagnostic procedures that make a single fault assumption may give an incorrect diagnosis. In this paper, a systematic approach is proposed for delay fault diagnosis under a multiple fault assumption. Information from the failing test vectors are used to construct a list of single and multiple fault suspects that may have caused all of the observed faulty response. The list of suspects is then pruned and ranked in a novel way by using information from the passing test vectors combined with static timing information.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128556424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Orphan metal removal as an element of DFM 残金属去除是DFM的一个元素
Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223) Pub Date : 1998-11-02 DOI: 10.1109/DFTVS.1998.732149
Neil Harrison
{"title":"Orphan metal removal as an element of DFM","authors":"Neil Harrison","doi":"10.1109/DFTVS.1998.732149","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732149","url":null,"abstract":"Discussion of improving the yield and manufacturability of designs through the modification of metal tracks has apparently neglected a potentially important first step-that of removal of metal which is surplus to the design. A technique is described for the identification and removal of surplus or 'orphan' metal using tools present in the Cadence layout system. Application of this technique to a semi-custom product designed in a 0.8 micron analog BiCMOS process is outlined.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125170240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A fast minimum layout perturbation algorithm for electromigration reliability enhancement 提高电迁移可靠性的快速最小布局摄动算法
Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223) Pub Date : 1998-11-02 DOI: 10.1109/DFTVS.1998.732151
Zhan Chen, Fook-Luen Heng
{"title":"A fast minimum layout perturbation algorithm for electromigration reliability enhancement","authors":"Zhan Chen, Fook-Luen Heng","doi":"10.1109/DFTVS.1998.732151","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732151","url":null,"abstract":"Electromigration (EM) is a major failure mechanism in today's deep-submicron VLSI circuits. It has become more so due to increasingly smaller circuit wires and higher current density. The most direct and effective method to reduce the EM susceptibility of a circuit is to increase the width of wires that have high current density. Wire widening in a layout implies that interacting layout elements need to be adjusted in order to accommodate the widened wires. In this paper, we study the problem of automatic widening of wires with high current density in a completed layout. We use the minimum layout perturbation criteria when adjusting the positions of layout elements to preserve as much structure of the layout as possible and propose a fast heuristic based on a single error removal algorithm. Our experiments show that the fast heuristic is very suitable for widening wires to enhance EM reliability and the new algorithm is 4x-10x faster than a general purpose graph-based simplex (GBS) solver for the general minimum layout perturbation problem.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"107 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131388483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
BIST module for mixed-signal circuits 用于混合信号电路的BIST模块
Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223) Pub Date : 1998-11-02 DOI: 10.1109/DFTVS.1998.732185
S. Demidenko, V. Piuri, V. Yarmolik, A. Shmidman
{"title":"BIST module for mixed-signal circuits","authors":"S. Demidenko, V. Piuri, V. Yarmolik, A. Shmidman","doi":"10.1109/DFTVS.1998.732185","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732185","url":null,"abstract":"T-flip-flop implementation of the universal module (signature analyzer and test generator) for built-in self-test of mixed signal circuits is proposed and analyzed.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132603814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Highly reliable systems with differential built-in current sensors 高度可靠的系统，内置差分电流传感器
Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223) Pub Date : 1998-11-02 DOI: 10.1109/DFTVS.1998.732174
Jien-Chung Lo
{"title":"Highly reliable systems with differential built-in current sensors","authors":"Jien-Chung Lo","doi":"10.1109/DFTVS.1998.732174","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732174","url":null,"abstract":"A duplicated system with a differential built-in current sensor (DBICS) method is proposed in this paper as an alternative to the classical TMR designs. The DBICS compares the I/sub DDQ/ levels of the two copies from a duplicated system and then selects the correct output. Unlike the previously known duplicated-with-self-checking scheme, the proposed method is easy to design and to implement. Further, the system block can be either combinational or sequential circuits and whose size is limited only by the capability of the BICS. The extremely low redundancy level of the proposed method, /spl ap/1% or less, enables a very high reliability performance, more than any existing technique. As the failure rates of modern submicron and deep sub-micron VLSI chips are increasing, the proposed technique will allow the use of modern high-performance chips in highly critical applications.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133344335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Accurate fault modeling and fault simulation of resistive bridges 电阻式电桥的精确故障建模与故障仿真
Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223) Pub Date : 1998-11-02 DOI: 10.1109/DFTVS.1998.732156
V. Sar-Dessai, D. Walker
{"title":"Accurate fault modeling and fault simulation of resistive bridges","authors":"V. Sar-Dessai, D. Walker","doi":"10.1109/DFTVS.1998.732156","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732156","url":null,"abstract":"This paper presents accurate fault models, an accurate fault simulation technique, and a new fault coverage metric for resistive bridging faults in gate level combinational circuits at nominal and reduced power supply voltages. We show that some faults have unusual behavior, which has been observed in practice. On the ISCAS85 benchmark circuits we show that a zeroohm bridge fault model can be quite optimistic in terms of coverage of voltage-testable bridging faults.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122464537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
High-level BIST synthesis for delay testing 用于延迟测试的高水平BIST综合
Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223) Pub Date : 1998-11-02 DOI: 10.1109/DFTVS.1998.732181
Xiaowei Li, P. Cheung
{"title":"High-level BIST synthesis for delay testing","authors":"Xiaowei Li, P. Cheung","doi":"10.1109/DFTVS.1998.732181","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732181","url":null,"abstract":"As delay testing using an external tester requires expensive test equipment, BIST is an alternative technique that can significantly reduce the test cost. A prime concern in using BIST is the area overhead due to the modifications of normal registers to be test registers. This paper presents a BIST TPG scheme for the detection of delay faults. This scheme produces single-input change test-pair sequence which guarantees the detection of all testable path delay faults. In order to implement the proposed BIST scheme effectively, this paper exploits high-level synthesis process, and presents a data path allocation approach, which results in a minimum area BIST solution. The proposed BIST scheme and the register assignment approach were applied to academic benchmarks.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125233864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Designing for yield: a defect-tolerant approach to high-level synthesis 为产量而设计:高水平合成的容错方法
Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223) Pub Date : 1998-11-02 DOI: 10.1109/DFTVS.1998.732180
M. Broglia, G. Buonanno, M. Sami, M. Selvini
{"title":"Designing for yield: a defect-tolerant approach to high-level synthesis","authors":"M. Broglia, G. Buonanno, M. Sami, M. Selvini","doi":"10.1109/DFTVS.1998.732180","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732180","url":null,"abstract":"Defect-tolerant techniques can be effectively applied to regular structures which allow a very simple reconfiguration technique. A typical example is represented by memories, where algorithms for row and column elimination grant very good results with a limited area overhead (namely, a limited number of spare rows and columns). The reconfiguration technologies developed for memories could be applied to other devices only if the two conditions of regularity and simplicity can be transferred to their architectures. In the present paper we propose a methodology aiming at designing an intrinsically regular data path thus achieving defect-tolerance with a limited area increase, both in terms of spare functional units and memories and in terms of augmented interconnection network.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128056289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Binning for IC quality: experimental studies on the SEMATECH data 集成电路质量分级:SEMATECH数据的实验研究
Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223) Pub Date : 1998-11-02 DOI: 10.1109/DFTVS.1998.732145
A. Singh, D. Lakin, Gaurav Sinha, P. Nigh
{"title":"Binning for IC quality: experimental studies on the SEMATECH data","authors":"A. Singh, D. Lakin, Gaurav Sinha, P. Nigh","doi":"10.1109/DFTVS.1998.732145","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732145","url":null,"abstract":"In semiconductor manufacturing, the observed clustering of defects on a wafer has often led to the practice of discarding die from wafers, or parts of the wafer, that display a high incidence of failures. In recent work we have formalized and refined this process with the goal of minimizing test escapes during production testing. In the new approach, in evaluating the quality of test results for a particular die, test results for the die's neighbors are also considered. Among other results, it has been shown that by exploiting defect clustering information it is possible to bin dice following testing so as to separate out a high quality bin with defect levels up to an order of magnitude better than the average for the lot. In this paper we present the first experimental results on the effectiveness of die screening for a modern submicron CMOS process. The data comes from the SEMATECH test methods experiment conducted at IBM on 18,466 from a production ASIC in a 0.5 /spl mu/m process.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124534032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
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