{"title":"多时延故障的系统诊断方法","authors":"Jayabrata Ghosh-Dastidar, N. Touba","doi":"10.1109/DFTVS.1998.732168","DOIUrl":null,"url":null,"abstract":"In the presence of multiple delay faults, automated diagnostic procedures that make a single fault assumption may give an incorrect diagnosis. In this paper, a systematic approach is proposed for delay fault diagnosis under a multiple fault assumption. Information from the failing test vectors are used to construct a list of single and multiple fault suspects that may have caused all of the observed faulty response. The list of suspects is then pruned and ranked in a novel way by using information from the passing test vectors combined with static timing information.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"25","resultStr":"{\"title\":\"A systematic approach for diagnosing multiple delay faults\",\"authors\":\"Jayabrata Ghosh-Dastidar, N. Touba\",\"doi\":\"10.1109/DFTVS.1998.732168\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In the presence of multiple delay faults, automated diagnostic procedures that make a single fault assumption may give an incorrect diagnosis. In this paper, a systematic approach is proposed for delay fault diagnosis under a multiple fault assumption. Information from the failing test vectors are used to construct a list of single and multiple fault suspects that may have caused all of the observed faulty response. The list of suspects is then pruned and ranked in a novel way by using information from the passing test vectors combined with static timing information.\",\"PeriodicalId\":245879,\"journal\":{\"name\":\"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)\",\"volume\":\"25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-11-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"25\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DFTVS.1998.732168\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFTVS.1998.732168","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A systematic approach for diagnosing multiple delay faults
In the presence of multiple delay faults, automated diagnostic procedures that make a single fault assumption may give an incorrect diagnosis. In this paper, a systematic approach is proposed for delay fault diagnosis under a multiple fault assumption. Information from the failing test vectors are used to construct a list of single and multiple fault suspects that may have caused all of the observed faulty response. The list of suspects is then pruned and ranked in a novel way by using information from the passing test vectors combined with static timing information.