A fast minimum layout perturbation algorithm for electromigration reliability enhancement

Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223) Pub Date : 1998-11-02 DOI:10.1109/DFTVS.1998.732151

Zhan Chen, Fook-Luen Heng

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引用次数: 5

Abstract

Electromigration (EM) is a major failure mechanism in today's deep-submicron VLSI circuits. It has become more so due to increasingly smaller circuit wires and higher current density. The most direct and effective method to reduce the EM susceptibility of a circuit is to increase the width of wires that have high current density. Wire widening in a layout implies that interacting layout elements need to be adjusted in order to accommodate the widened wires. In this paper, we study the problem of automatic widening of wires with high current density in a completed layout. We use the minimum layout perturbation criteria when adjusting the positions of layout elements to preserve as much structure of the layout as possible and propose a fast heuristic based on a single error removal algorithm. Our experiments show that the fast heuristic is very suitable for widening wires to enhance EM reliability and the new algorithm is 4x-10x faster than a general purpose graph-based simplex (GBS) solver for the general minimum layout perturbation problem.

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提高电迁移可靠性的快速最小布局摄动算法

电迁移(EM)是当今深亚微米VLSI电路的主要失效机制。由于越来越小的电路线和更高的电流密度，它变得更加如此。降低电路电磁磁化率最直接有效的方法是增加高电流密度导线的宽度。布局中的导线扩展意味着需要调整相互作用的布局元素，以适应导线的扩展。本文研究了在完整布线中，高电流密度导线的自动加宽问题。在调整布局元素位置时，采用最小布局扰动准则，尽可能多地保留布局的结构，并提出了一种基于单一误差去除算法的快速启发式算法。我们的实验表明，快速启发式算法非常适合于扩大电线以提高电磁可靠性，并且新算法比一般最小布局扰动问题的通用基于图的单纯形(GBS)求解器快4 -10倍。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)

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