{"title":"Systematic AUED codes for self-checking architectures","authors":"D. Sciuto, C. Silvano, R. Stefanelli","doi":"10.1109/DFTVS.1998.732165","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732165","url":null,"abstract":"Encoding techniques and dedicated self-checking architectures can be conveniently adopted in VLSI design to increase fault detection. Area overhead and speed penalty may be traded-off with fault detection capabilities. Aim of this work is to define a class of systematic all-unidirectional error-detecting (AUED) codes suitable for self-checking architectures for multiple output combinational circuits. A class of systematic AUED codes is proposed along with a logic synthesis algorithm to derive the redundant functions directly from the primary inputs. If compared with Berger codes, the proposed encoding techniques require greater output redundancy but provide performance optimization in terms of both transition delays and area overhead.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134016359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Reducing fault sensitivity of microprocessor-based systems by modifying workload structure","authors":"D. Audet, S. Masson, Y. Savaria","doi":"10.1109/DFTVS.1998.732172","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732172","url":null,"abstract":"The use of off-the-shelf components in microprocessor-based systems can limit the applicability of a number of hardware fault-tolerance methods. Software techniques offer attractive solutions to improve the reliability of systems operating in a hostile environment. The fault sensitivity of a system running a critical application obviously depends on the application execution time and the amount of memory it uses. This study shows that the program structure also has a significant influence on fault sensitivity. Program characteristics, such as the size and duration of iterative and sequential sections, are required to determine the sensitivity profile. It is shown that, provided data dependency is not affected one can rearrange the program structure to significantly reduce the average sensitivity of a program. Straightforward analysis of the sensitivity profile allows one to estimate the reduction. A simple example of code rearrangement is described and it is shown that a 50% reduction could be achieved with respect to the initial structure. The magnitude of the reduction varies from one application to another.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132040173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Yield and routing objectives in floorplanning","authors":"I. Koren, Z. Koren","doi":"10.1109/DFTVS.1998.732148","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732148","url":null,"abstract":"Traditionally the floorplan of a chip has been determined so as to minimize the total chip area and reduce the routing costs. Recently, it has been shown that the floorplan also affects the yield of the chip. Consequently, it becomes desirable to consider the expected yield, in addition to the cost of routing, when selecting a floorplan. The goal of this paper is to study the two seemingly disjoint objectives of yield enhancement and routing complexity minimization, and find out whether they lead to different optimal floorplans, resulting in a need for a tradeoff analysis.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"349 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127662310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Transient and intermittent fault recovery without rollback","authors":"S. Hamilton, A. Orailoglu","doi":"10.1109/DFTVS.1998.732173","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732173","url":null,"abstract":"Increasing chip density combined with heightened reliability expectations has spawned greater interest in fault tolerant design. In recent years, research into rollback and retry techniques has established them as an effective approach to recovery from transient and intermittent faults. For applications with strict timing requirements, however, the high error latency inherent in retry approaches is unacceptable. We have developed an alternative recovery method with strict error latency boundaries. In addition, the bulky state storage hardware required in rollback designs has been eliminated. The result is a more efficient, more broadly applicable approach to fault tolerant design.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122988827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Self-reconfiguration scheme of 3D-mesh arrays","authors":"S. Horiguchi, I. Numata","doi":"10.1109/DFTVS.1998.732176","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732176","url":null,"abstract":"Addresses a self-reconfiguration scheme of 3D-mesh arrays. The reconfiguration performance of 3D-mesh is obtained for 3D 1 1/2 . We demonstrated that the proposed HS-scheme achieves high system yield without global information. Although 2D-mesh with 8000 PEs requires much more than 90 x 90 PEs, 3D-mesh array becomes a compact size of arrays. It is seen that the HS-scheme dose not achieve high array yield for a large size ED-mesh since the number of tracks is limited. However, the HS-scheme can be widely applied to 3D-mesh consisting of more PEs, more spare PEs, and more tracks, although other schemes are only for 3D 1 1/2.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128691594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. D'Angelo, C. Metra, S. Pastore, A. Pogutz, G. Sechi
{"title":"Fault-tolerant voting mechanism and recovery scheme for TMR FPGA-based systems","authors":"S. D'Angelo, C. Metra, S. Pastore, A. Pogutz, G. Sechi","doi":"10.1109/DFTVS.1998.732171","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732171","url":null,"abstract":"This paper presents an original approach to the implementation of a fault-tolerant FPGA-based system. In particular, we consider the conventional Triple Modular Redundancy fault-tolerance technique and address practical problems related to its actual implementation into FPGA devices. All possible functional faults affecting the used FPGAs are either tolerated or on-line detected. Differently from conventional VLSI fault-tolerant systems, here the FPGA possible reconfigurability is exploited to ensure the continuity of operation for a high number of possible internal faults, without requiring further replications (besides the three basic copies) of the considered device.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128163989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Yield enhancement by multi-level linear modeling of non-idealities in an interpolated flash ADC","authors":"A. Boni, A. Pierazzi","doi":"10.1109/DFTVS.1998.732182","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732182","url":null,"abstract":"The paper discusses a diagnostic technique for interpolated flash A/D converters based on a multi-level linear model. It allows identification of non-ideality sources, such as layout imperfections or thermal gradients, in the first silicon and provides guidance for the improvement of yield by layout refinement, thus outperforming Monte Carlo techniques which do not usually account for layout-related issues.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125654402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An integrated HW and SW fault injection environment for real-time systems","authors":"A. Benso, M. Rebaudengo, M. Reorda, P. Civera","doi":"10.1109/DFTVS.1998.732158","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732158","url":null,"abstract":"This paper describes a system suited to support the Fault Injection process for microprocessor-based embedded systems. The system exploits a low-cost hardware board to monitor the processor status, to activate the fault injection procedure, and to gather information about the fault-free system behavior required to implement a set of fault collapsing rules. The overall environment allows at-speed fault injection experiments with negligible intrusiveness in the target system, and can therefore be used to efficiently evaluate real-time systems dependability.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"2003 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128289190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Characterization of CMOS defects using transient signal analysis","authors":"J. Plusquellic, D. Chiarulli, S. Levitan","doi":"10.1109/DFTVS.1998.732155","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732155","url":null,"abstract":"We present the results of hardware experiments designed to determine the relative contribution of CMOS coupling mechanisms to off-path signal variations caused by common types of defects. The transient signals measured in defect-free test structures coupled to defective test structures through internodal coupling capacitors, the power supply, the well and substrate are analyzed in the time and frequency domain to determine the characteristics of the signal variations produced by seven types of CMOS defects. The results of these experiments are used in the development of a failure analysis technique based on the analysis of transient signals.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115870070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Challenges of built-in current sensor designs","authors":"Yu-Yau Guo, Jien-Chung Lo","doi":"10.1109/DFTVS.1998.732166","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732166","url":null,"abstract":"Built-in current sensors (BICSs) are very useful for both off-line and on-line testing. However, the practical use of BICS remains illusive due to several major concerns. This paper addresses the trade-off in design considerations and with examples from the existing designs. We then present a new BICS design which we believe can be easily incorporated into design automation process. Assuming that the CUT has been equipped with a voltage regulator, the proposed BICS obtains the I/sub DDQ/ sample from the voltage regulator directly and non-destructively. The insertion of the proposed BICS can be easily automated due to its simplicity.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117052479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}