Yield and routing objectives in floorplanning

Abstract

Traditionally the floorplan of a chip has been determined so as to minimize the total chip area and reduce the routing costs. Recently, it has been shown that the floorplan also affects the yield of the chip. Consequently, it becomes desirable to consider the expected yield, in addition to the cost of routing, when selecting a floorplan. The goal of this paper is to study the two seemingly disjoint objectives of yield enhancement and routing complexity minimization, and find out whether they lead to different optimal floorplans, resulting in a need for a tradeoff analysis.