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Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)最新文献

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A new method for testing EEPLAs 一种测试eepla的新方法
Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223) Pub Date : 1998-11-02 DOI: 10.1109/DFTVS.1998.732161
A. Munshi, F. Meyer, F. Lombardi
{"title":"A new method for testing EEPLAs","authors":"A. Munshi, F. Meyer, F. Lombardi","doi":"10.1109/DFTVS.1998.732161","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732161","url":null,"abstract":"We present a new method for testing electrically erasable programmable logic arrays (EEPLA) under multiple faults. These include line stuck-at faults, bridging faults, and crosspoint faults. Our proposed method achieves 100% fault coverage of multiple faults by reprogramming the EEPLA many times. The complexity of testing EEPLAs is largely dependent on the number of programming phases, because programming time is much larger than test application time. The proposed method achieves a substantial reduction in programming phases compared with prior methods; and, thereby, in testing time, even though it involves more test vectors. The programming is based on a parallel sequence in which a larger number of crosspoints are tested per phase-a toroidal sequence with which full coverage is still guaranteed. We analyze the method to obtain the testing time as a function of the numbers of input variables, product lines, and output functions.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121898789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A comparison of efficient dot throwing and shape shifting extra material critical area estimation 高效抛点与变形法的额外材料临界面积估算比较
Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223) Pub Date : 1998-11-02 DOI: 10.1109/DFTVS.1998.732150
G. A. Allan
{"title":"A comparison of efficient dot throwing and shape shifting extra material critical area estimation","authors":"G. A. Allan","doi":"10.1109/DFTVS.1998.732150","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732150","url":null,"abstract":"The paper reports a comparison of efficient methods of estimating extra material critical area of any angled IC layout using two different techniques, shape shifting and dot throwing. Both techniques are implemented using the same polygon libraries and are optimised to make best use of the library features. This allows an accurate comparison of the techniques with minimal dependence on the specific implementation. The results presented here suggest that for general yield prediction an efficient dot throwing implementation is best suited for layouts of any significant size (designs greater than 1 MB of layout data). However, the shape shifting technique is considerably more efficient in the analysis of smaller circuits but does not scale well to larger designs.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130330377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
High-level synthesis of data paths with concurrent error detection 具有并发错误检测的高级数据路径综合
Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223) Pub Date : 1998-11-02 DOI: 10.1109/DFTVS.1998.732178
A. Antola, V. Piuri, M. Sami
{"title":"High-level synthesis of data paths with concurrent error detection","authors":"A. Antola, V. Piuri, M. Sami","doi":"10.1109/DFTVS.1998.732178","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732178","url":null,"abstract":"High-level synthesis of data paths with concurrent self-checking abilities is discussed to balance redundancy, latency, and checking effectiveness. The nominal and the checking computations are scheduled and allocated contemporaneously by using a force-directed approach to limit the number of redundant units required to achieve detection within the latency of the nominal computation only. Resource sharing between the nominal and the checking computation is used to minimise the redundancy, while keeping error aliasing as reduced as possible.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114204406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
A silicon compiler for fault-tolerant ROMs 用于容错rom的硅编译器
Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223) Pub Date : 1998-11-02 DOI: 10.1109/DFTVS.1998.732175
Anurag P. Gupta, K. Chakraborty, P. Mazumder
{"title":"A silicon compiler for fault-tolerant ROMs","authors":"Anurag P. Gupta, K. Chakraborty, P. Mazumder","doi":"10.1109/DFTVS.1998.732175","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732175","url":null,"abstract":"This paper describes a new CAD tool, FTROM-Fault-Tolerant ROM-compiler, for synthesizing fault-tolerant ROM modules with flexible, user-specified geometry and CMOS design-rule parameters. It employs a novel fault-tolerant design approach that produces negligible access delay penalty and silicon area overhead. FTROM reduces the design turnaround time and the BIST and BISR circuitry incorporated eliminate the high cost of external testing of commodity ROMs. Such circuits are also very useful for on-chip ROM macrocells used in high-density microprocessors and ASICs, since the I/O pins of such macrocells are extremely difficult to control and observe.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124352584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
C-testable one-dimensional ILAs with respect to path delay faults: theory and applications 关于路径延迟故障的c可测试一维集成电路:理论与应用
Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223) Pub Date : 1998-11-02 DOI: 10.1109/DFTVS.1998.732162
T. Haniotakis, D. Nikolos, Y. Tsiatouhas
{"title":"C-testable one-dimensional ILAs with respect to path delay faults: theory and applications","authors":"T. Haniotakis, D. Nikolos, Y. Tsiatouhas","doi":"10.1109/DFTVS.1998.732162","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732162","url":null,"abstract":"In this paper we give, for first time in the open literature, sufficient conditions so that a one-dimensional iterative-logic-array (ILA) is C-testable taking into account the path delay fault model. We give also a method for path selection so as all the selected paths can be tested by a constant number of test-vector pairs. The delay of all other paths is a function of the delays of the selected paths. As example, we consider the ripple-carry adder and the group carry look ahead adder with ripple carry between groups.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125754262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Graceful degradation in synthesis of VLSI ICs VLSI集成电路合成中的优雅退化
Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223) Pub Date : 1998-11-02 DOI: 10.1109/DFTVS.1998.732179
A. Orailoglu
{"title":"Graceful degradation in synthesis of VLSI ICs","authors":"A. Orailoglu","doi":"10.1109/DFTVS.1998.732179","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732179","url":null,"abstract":"Increasing levels of societal reliance on computerized solutions demand fault-resilient solutions. At the same time, system-on-a-chip levels of integration, demand a reexamination and migration of traditional system level fault resilience techniques to the integrated circuit level. Automated synthesis methodologies need to provide embedded, low-cost fault resilience properties, capable of ensuring fault resilience for all on-chip components and interconnects. The outlined approaches in this paper pioneer the insertion of unabridged fault resilience properties at the IC level through highly automated approaches. The experimental results show cost-effective solutions, with no performance degradation, in the synthesized ASICs.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134533377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Error-correcting Goldschmidt dividers using time shared TMR 使用分时TMR纠错的Goldschmidt分频器
Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223) Pub Date : 1998-11-02 DOI: 10.1109/DFTVS.1998.732170
W. Gallagher, E. Swartzlander
{"title":"Error-correcting Goldschmidt dividers using time shared TMR","authors":"W. Gallagher, E. Swartzlander","doi":"10.1109/DFTVS.1998.732170","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732170","url":null,"abstract":"Several implementations of division are based on the Goldschmidt, or series expansion, algorithm. It has a number of advantages, including quadratic convergence to the solution and two independent, and hence pipelinable, multiplies per iteration. Applying time shared triple modular redundancy (TSTMR) to such a divider allows the use of a smaller multiplier and requires triplicating the divider circuit. The smaller multiplier completes larger multiplications in several cycles using feedback registers. While this reduces the size of the fault tolerant divider over that of traditional TMR, there is a substantial penalty to latency. However, because early stages of the algorithm do not require high-precision multiplications, and rounding the quotient by computing the inverse function does not require a full-precision multiplication, the algorithm can be modified to reduce multiplication cycles. The resulting error-correcting dividers can be both faster and smaller than fault-tolerant dividers using traditional TMR.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114882642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Modular fault simulation of mixed signal circuits with fault ranking by severity 基于严重程度排序的混合信号电路模块化故障仿真
Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223) Pub Date : 1998-11-02 DOI: 10.1109/DFTVS.1998.732184
A. Gomes, R. Voorakaranam, A. Chatterjee
{"title":"Modular fault simulation of mixed signal circuits with fault ranking by severity","authors":"A. Gomes, R. Voorakaranam, A. Chatterjee","doi":"10.1109/DFTVS.1998.732184","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732184","url":null,"abstract":"In this paper, we propose a novel approach to fault simulation of large mixed signal circuits using circuit partitioning and fault ordering. The conventional statistical fault model is divided, to separately account for global and local variations. We consider the problem of estimating the effect of a parameter deviation in a sub-module, on the system level specifications for a general nonlinear circuit. This method uses a function approximation model to estimate the system response and rank the faults according to the severity. Applications of this algorithm include estimation of fault coverage and forms a key element in test generation and diagnosis procedures.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128489023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
On the complexity of sequential testing in configurable FPGAs 论可配置fpga中顺序测试的复杂性
Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223) Pub Date : 1998-11-02 DOI: 10.1109/DFTVS.1998.732163
Wenyi Feng, F. Meyer, Wei-Kang Huang, F. Lombardi
{"title":"On the complexity of sequential testing in configurable FPGAs","authors":"Wenyi Feng, F. Meyer, Wei-Kang Huang, F. Lombardi","doi":"10.1109/DFTVS.1998.732163","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732163","url":null,"abstract":"This paper addresses the issues pertaining to testing field programmable gate arrays (FPGAs) using an array-based technique. In particular, the issues of testing configurable devices (such as multiplexers and flip-flops) in the sequential array process (as the most significant factor for assessing complexity) and the arrangement for pipelining test vectors are treated in detail. Initially testing procedures for a configurable flip-flop and a programmable multiplexer are presented. At system-level, two new pipeline arrangements referred to as the quasi-pipeline and normal pipeline structures are proposed for reducing the number of programming phases. The application of the proposed approaches to the XC4000 FPGA family is also presented.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127098659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Can the current behavior of faulty and fault-free ICs and the impact on diagnosis ic故障和无故障的当前行为和对诊断的影响
Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223) Pub Date : 1998-11-02 DOI: 10.1109/DFTVS.1998.732167
C. Thibeault, L. Boisvert
{"title":"Can the current behavior of faulty and fault-free ICs and the impact on diagnosis","authors":"C. Thibeault, L. Boisvert","doi":"10.1109/DFTVS.1998.732167","DOIUrl":"https://doi.org/10.1109/DFTVS.1998.732167","url":null,"abstract":"The purpose of this paper is to analyze the current behavior of faulty and fault free integrated circuits (ICs) and its impact on diagnosis. More specifically, we first show that normal sub-threshold current can be modeled by a Gaussian distribution. Then, we investigate faulty IC current variations caused to the load connected to nodes involved in bridging faults. Finally, we propose some modifications to a diagnosis method based on maximum likelihood estimation to deal with these behaviors.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130430988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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