关于路径延迟故障的c可测试一维集成电路:理论与应用

Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223) Pub Date : 1998-11-02 DOI:10.1109/DFTVS.1998.732162

T. Haniotakis, D. Nikolos, Y. Tsiatouhas

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引用次数: 9

摘要

本文首次在公开文献中给出了考虑路径延迟故障模型的一维迭代逻辑阵列(ILA)可c测试的充分条件。我们还给出了一种路径选择方法，使得所有选择的路径都可以用常数对测试向量进行测试。所有其他路径的延迟是所选路径延迟的函数。作为例子，我们考虑了波纹进位加法器和组间带波纹进位的群进位前置加法器。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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C-testable one-dimensional ILAs with respect to path delay faults: theory and applications

In this paper we give, for first time in the open literature, sufficient conditions so that a one-dimensional iterative-logic-array (ILA) is C-testable taking into account the path delay fault model. We give also a method for path selection so as all the selected paths can be tested by a constant number of test-vector pairs. The delay of all other paths is a function of the delays of the selected paths. As example, we consider the ripple-carry adder and the group carry look ahead adder with ripple carry between groups.

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Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)

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