A new method for testing EEPLAs

A. Munshi, F. Meyer, F. Lombardi
{"title":"A new method for testing EEPLAs","authors":"A. Munshi, F. Meyer, F. Lombardi","doi":"10.1109/DFTVS.1998.732161","DOIUrl":null,"url":null,"abstract":"We present a new method for testing electrically erasable programmable logic arrays (EEPLA) under multiple faults. These include line stuck-at faults, bridging faults, and crosspoint faults. Our proposed method achieves 100% fault coverage of multiple faults by reprogramming the EEPLA many times. The complexity of testing EEPLAs is largely dependent on the number of programming phases, because programming time is much larger than test application time. The proposed method achieves a substantial reduction in programming phases compared with prior methods; and, thereby, in testing time, even though it involves more test vectors. The programming is based on a parallel sequence in which a larger number of crosspoints are tested per phase-a toroidal sequence with which full coverage is still guaranteed. We analyze the method to obtain the testing time as a function of the numbers of input variables, product lines, and output functions.","PeriodicalId":245879,"journal":{"name":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFTVS.1998.732161","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

Abstract

We present a new method for testing electrically erasable programmable logic arrays (EEPLA) under multiple faults. These include line stuck-at faults, bridging faults, and crosspoint faults. Our proposed method achieves 100% fault coverage of multiple faults by reprogramming the EEPLA many times. The complexity of testing EEPLAs is largely dependent on the number of programming phases, because programming time is much larger than test application time. The proposed method achieves a substantial reduction in programming phases compared with prior methods; and, thereby, in testing time, even though it involves more test vectors. The programming is based on a parallel sequence in which a larger number of crosspoints are tested per phase-a toroidal sequence with which full coverage is still guaranteed. We analyze the method to obtain the testing time as a function of the numbers of input variables, product lines, and output functions.
一种测试eepla的新方法
提出了一种在多重故障下测试电可擦可编程逻辑阵列(EEPLA)的新方法。这些故障包括线路卡故障、桥接故障和交叉点故障。该方法通过对EEPLA进行多次重编程,实现了对多个故障100%的故障覆盖率。测试eepla的复杂性很大程度上取决于编程阶段的数量,因为编程时间比测试应用程序时间要长得多。与先前的方法相比,所提出的方法大大减少了编程阶段;因此,在测试时间里,即使它涉及到更多的测试向量。编程是基于一个并行序列,在这个并行序列中,每个相位测试更多的交叉点——一个环面序列,它仍然保证完全覆盖。我们分析了该方法,以获得测试时间作为输入变量,产品线和输出函数的数量的函数。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信